Semiconductor image sensor

Claim 2

A semiconductor image pick-up device comprising: first and second photodetectors; a first pair of field-effect transistors having their sources connected to said first photodetector; a second pair of field-effect transistors having their sources connected to said second photodetector; a first output line which interconnects the drains of each respective one of the transistors of said first and second pairs of field-effect transistors; a second output line which interconnects the drains of each respective other of the transistors of said first and second pairs of field-effect transistors; an input line which interconnects the gate of the one transistor of said first pair of transistors to the gate of the other transistor of said second pair of transistors; first circuit means which is connected to said first and second output lines for generating a signal representative of the difference of signals appearing on said first and second output lines; and second circuit means for applying a signal readout pulse to said input line when said first photodetector has no optical input stored therein.

Claim 3

A semiconductor image pick-up device according to claim 1, wherein said photodetectors comprise photodiodes the ends of which, opposite the sources of the field-effect transistors to which they are connected, are connected to a source of reference potential.

Claim 4

A semiconductor image pick-up device according to claim 1, wherein each of said photodetectors and field-effect transistors is integrated in a common substrate.

Claim 5

A semiconductor image pick-up device comprising: at least one column of image pick-up elements which includes: first to n th photodetectors, where n is an integer greater than two; first to n th pairs of field-effect transistors the sources of each transistor of each respective first to n th pair being connected to said first to n photodetectors; a first output line which interconnects the drains of each respective one of the transistors of said first to (n-1) th pairs of field-effect transistors; a second output line which interconnects the drains of each respective other of the transistors of said first to n th pairs of field-effect transistors; a first input line which is connected to the gate of the other of the transistors of said first pair of field-effect transistors; second to n th input lines which interconnect the gates of each of the transistors of said first to (n-1) th pairs of field-effect transistors to the gates of each other of the transistors of said second n th pairs of field-effect transistors, respectively; an (n+1) th input line which is connected to the gate of one of the transistors of said n th pair of field-effect transistors; a differential amplifier circuit connected to said first and second output lines; and circuit means for applying signal readout pulses sequentially to said first to n th lines.

Claim 6

A semiconductor image pick-up device comprising: at least one column of image pick-up elements which includes: first to n th photodetectors, where n is an integer greater than two; first to n th pairs of field-effect transistors the sources of each transistor of each respective first to n th pair being connected to said first to n photodetectors; a first output line which interconnects the drains of each respective one of the transistors of said first to (n-1) th pairs of field-effect transistors; a second output line which interconnects the drains of each respective other of the transistors of said first to n th pairs of field-effect transistors; a first input line which is connected to the gate of the other of the transistors of said first pair of field-effect transistors; second to n th input lines which interconnect the gates of each of the transistors of said first to (n-1) th pairs of field-effect transistors to the gates of each other of the transistors of said second n th pairs of field-effect transistors, respectively; an (n+1) th input line which is connected to the gate of one of the transistors of said n th pair of field-effect transistors; a differential amplifier circuit connected to said first and second output lines; and circuit means for applying signal readout pulses sequentially to said first to n th lines.

Claim 7

A semiconductor image pick-up device according to claim 4, where said at least one column comprises m of said columns, where m is an integer greater than one, the respective, and first to (n+1) th input lines of each column being connected together, so as to form a matrix of image pick-up elements.

Claim 8

A semiconductor image pick-up device comprising at least one column of image pick-up elements which includes: first to n th photodetectors, where n is an integer greater than two, first to n th pairs of field-effect transistors, the source of each transistor of each respective first to n th pair being connected to said first to n th photodetectors; first and second auxiliary photodetectors, first and second auxiliary field effect transistors the sources of which are respectively connected to said first and second auxiliary photodetectors, a first output line which interconnects the drains of each respective one of the transistors of said first to n th pairs of field-effect transistors and the drain of said first auxiliary field-effect transistor, a second output line which interconnects the drains of each respective other of the transistors of said first to n th pairs of field-effect transistors and the drain of said second auxiliary field-effect transistor. a first input line which interconnects the gate of said first auxiliary field-effect transistor and the gate of the other transistor of said first pair of field-effect transistors, second to n th input lines which interconnect the gates of each respective one of the transistors of said first to (n-1) th pairs of field-effect transistors and the gates of each respective other of the transistors of said second to n th pairs of field effect transistors, respectively, a clearing drive line which interconnects the gate of the one of the transistors of said n th pair of field-effect transistors and the gate of said second auxiliary field-effect transistor, and a differential amplifier circuit connected to said first and second output lines; and circuit means for applying signal readout pulses sequentially to said first to n th input lines.

Claim 9

A semiconductor image pick-up device comprising at least one column of image pick-up elements which includes: first to n th photodetectors, where n is an integer greater than two, first to n th pairs of field-effect transistors, the source of each transistor of each respective first to n th pair being connected to said first to n th photodetectors; first and second auxiliary photodetectors, first and second auxiliary field effect transistors the sources of which are respectively connected to said first and second auxiliary photodetectors, a first output line which interconnects the drains of each respective one of the transistors of said first to n th pairs of field-effect transistors and the drain of said first auxiliary field-effect transistor, a second output line which interconnects the drains of each respective other of the transistors of said first to n th pairs of field-effect transistors and the drain of said second auxiliary field-effect transistor. a first input line which interconnects the gate of said first auxiliary field-effect transistor and the gate of the other transistor of said first pair of field-effect transistors, second to n th input lines which interconnect the gates of each respective one of the transistors of said first to (n-1) th pairs of field-effect transistors and the gates of each respective other of the transistors of said second to n th pairs of field effect transistors, respectively, a clearing drive line which interconnects the gate of the one of the transistors of said n th pair of field-effect transistors and the gate of said second auxiliary field-effect transistor, and a differential amplifier circuit connected to said first and second output lines; and circuit means for applying signal readout pulses sequentially to said first to n th input lines.

Claim 10

A semiconductor image pick-up device according to claim 6, wherein said photodetectors comprise photodiodes the ends of which, opposite the sources of the field-effect transistors to which they are connected, are connected to a source of reference potential.

Claim 11

A semiconductor image pick-up device according to claim 6, where said at least one column comprises m of said columns, where m is an integer greater than one, the respective clearing drive line, and first to n th input lines of each column being connected together, so as to form a matrix of image pick-up elements.

Claim 12

A semiconductor image pick-up device according to claim 6, wherein each of said photodetectors and field-effect transistor is integrated in a common substrate.

Claim 13

A semiconductor image pick-up device comprising: a matrix of m rows by n columns of photodetectors, where m and n are positive integers greater than one and three, respectively; a matrix of m rows by n columns of field-effect transistors, the source of each respective transistor for each respective row and column being connected to the photodetector in that row and column; first to m th vertical address pulse input lines which interconnect the gates of the field-effect transistors of the first to m th rows, respectively; first to n th transmission lines which interconnect the drains of the field effect transistors of the first to n th columns; respectively; first, second and third field effect transistors, the sources of which are connected in common to said first transmission line; first to (n-2) th pairs of field effect transistors, the sources of which are connected in common to said second to (n-1) th transmission lines, respectively; fourth, fifth and sixth field-effect transistors, the sources of which are connected in common to said n th transmission line; a first output line which interconnects the drain of said second field-effect transistor, the drains of one of the transistors of said first to (n-2) th pairs of field-effect transistors, and the drains of said fourth and sixth field effect transistors; a second output line which interconnects the drains of said first and third field-effect transistors, the drains of the other of the transistors of said first to (n-2) th pairs of field-effect transistors, and the drain of said fifth field-effect transistors; a first horizontal address pulse input line which interconnects the gates of said first and second field-effect transistors; a second horizontal address pulse input line which interconnects the gate of said third field-effect transistor and the gate of the one transistor of said first pair of field-effect transistors; third to (n-1) th horizontal address pulse input lines which interconnect each respective gate of the other transistor of said first to (n-3) th pairs of field-effect transistors and each respective gate of the one of the transistors of said second to (n-2) th pairs of field-effect transistors, respectively; an n th horizontal address pulse input line which interconnects the gate of the other of the transistors of said (n-2) th pair of field-effect transistors and the gate of said fourth field-effect transistor; an (n+1) th horizontal address pulse input line which interconnects the gates of said fifth and sixth field effect transistors; a differential amplifier circuit connected to said first and second output lines; first circuit means for applying vertical address pulses sequentially to said first to m th vertical address pulse input lines; and second circuit means for applying horizontal address pulses sequentially to said first to (n+1) th horizontal address pulse input lines, so that the photodetectors of said matrix of photodetectors are sequentially subjected to readout.

Claim 14

A semiconductor image pick-up device comprising: a matrix of m rows by n columns of photodetectors, where m and n are positive integers greater than one and three, respectively; a matrix of m rows by n columns of field-effect transistors, the source of each respective transistor for each respective row and column being connected to the photodetector in that row and column; first to m th vertical address pulse input lines which interconnect the gates of the field-effect transistors of the first to m th rows, respectively; first to n th transmission lines which interconnect the drains of the field effect transistors of the first to n th columns; respectively; first, second and third field effect transistors, the sources of which are connected in common to said first transmission line; first to (n-2) th pairs of field effect transistors, the sources of which are connected in common to said second to (n-1) th transmission lines, respectively; fourth, fifth and sixth field-effect transistors, the sources of which are connected in common to said n th transmission line; a first output line which interconnects the drain of said second field-effect transistor, the drains of one of the transistors of said first to (n-2) th pairs of field-effect transistors, and the drains of said fourth and sixth field effect transistors; a second output line which interconnects the drains of said first and third field-effect transistors, the drains of the other of the transistors of said first to (n-2) th pairs of field-effect transistors, and the drain of said fifth field-effect transistors; a first horizontal address pulse input line which interconnects the gates of said first and second field-effect transistors; a second horizontal address pulse input line which interconnects the gate of said third field-effect transistor and the gate of the one transistor of said first pair of field-effect transistors; third to (n-1) th horizontal address pulse input lines which interconnect each respective gate of the other transistor of said first to (n-3) th pairs of field-effect transistors and each respective gate of the one of the transistors of said second to (n-2) th pairs of field-effect transistors, respectively; an n th horizontal address pulse input line which interconnects the gate of the other of the transistors of said (n-2) th pair of field-effect transistors and the gate of said fourth field-effect transistor; an (n+1) th horizontal address pulse input line which interconnects the gates of said fifth and sixth field effect transistors; a differential amplifier circuit connected to said first and second output lines; first circuit means for applying vertical address pulses sequentially to said first to m th vertical address pulse input lines; and second circuit means for applying horizontal address pulses sequentially to said first to (n+1) th horizontal address pulse input lines, so that the photodetectors of said matrix of photodetectors are sequentially subjected to readout.

Claim 15

A semiconductor image pick-up device according to claim 10, wherein said photodetectors comprise photodiodes the ends of which, opposite the sources of the field-effect transistors to which they are connected, are connected to a source of reference potential.

Claim 16

A semiconductor image pick-up device according to claim 10, wherein each of said photodetectors comprises a phototransistor, the emitter of which is connected to the source of a respective field effect transistor, and the collector of which is connected to a source of reference potential.

Claim 17

A semiconductor image pick-up device according to claim 12, wherein each of said photodetectors and field-effect transistor is integrated in a common substrate.

Claim 18

A semiconductor image pick-up device comprising: a matrix of m rows by n columns of photodetectors, where m and n are positive integers greater than one; a matrix of m rows by n columns of field-effect transistors, the source of each respective transistor for each respective row and column being connected to the photodetector in that respective row and column; first to m th vertical address pulse input lines which interconnect the gate of the field-effect transistors of the first to m th rows, respectively; first to n th transmission lines which interconnect the drains of the field-effect transistors of the first to n th columns, respectively; first to n th pairs of field-effect transistors, the sources of which are connected in common and are respectively connected to the first to n th transmission lines; a first output line which interconnects the drains of each respective one of the transistors of said first to n th pairs of field-effect transistors; a second output line which interconnects the drains of the other of the transistors of said first to n th pairs of field-effect transistors; a first horizontal address pulse input line connected to the gate of the one transistor of said first pair of field-effect transistors; a second horizontal address pulse input line which interconnects the gate of said other of the transistors of said first pair of field-effect transistors and the gate of the one of the transistors of said second pair of field-effect transistors; third to n th horizontal address pulse input lines which interconnect the gates of each respective other transistor of said second to (n-1) th pairs of field-effect transistors and the gates of each respective one transistor of said third to n th pairs of field-effect transistors, respectively; an (n+1) th horizontal address pule input line connected to the gate of the other transistor of said n th pair of field-effect transistors; a differential amplifier circuit connected to said first and second output lines; first circuit means for applying vertical address pulses sequentially to said first to m th vertical address pulse input lines; second circuit means for applying horizontal address pulses sequentially to said first to (n+1) th horizontal address pulse input lines; so that said matrix of m rows by n columns of photo-detectors are sequentially subjected to read-out.

Claim 19

A semiconductor image pick-up device comprising: a matrix of m rows by n columns of photodetectors, where m and n are positive integers greater than one; a matrix of m rows by n columns of field-effect transistors, the source of each respective transistor for each respective row and column being connected to the photodetector in that respective row and column; first to m th vertical address pulse input lines which interconnect the gate of the field-effect transistors of the first to m th rows, respectively; first to n th transmission lines which interconnect the drains of the field-effect transistors of the first to n th columns, respectively; first to n th pairs of field-effect transistors, the sources of which are connected in common and are respectively connected to the first to n th transmission lines; a first output line which interconnects the drains of each respective one of the transistors of said first to n th pairs of field-effect transistors; a second output line which interconnects the drains of the other of the transistors of said first to n th pairs of field-effect transistors; a first horizontal address pulse input line connected to the gate of the one transistor of said first pair of field-effect transistors; a second horizontal address pulse input line which interconnects the gate of said other of the transistors of said first pair of field-effect transistors and the gate of the one of the transistors of said second pair of field-effect transistors; third to n th horizontal address pulse input lines which interconnect the gates of each respective other transistor of said second to (n-1) th pairs of field-effect transistors and the gates of each respective one transistor of said third to n th pairs of field-effect transistors, respectively; an (n+1) th horizontal address pule input line connected to the gate of the other transistor of said n th pair of field-effect transistors; a differential amplifier circuit connected to said first and second output lines; first circuit means for applying vertical address pulses sequentially to said first to m th vertical address pulse input lines; second circuit means for applying horizontal address pulses sequentially to said first to (n+1) th horizontal address pulse input lines; so that said matrix of m rows by n columns of photo-detectors are sequentially subjected to read-out.

Claim 20

A semiconductor image pick-up device according to claim 14, wherein said photodetectors comprise photodiodes the ends of which, opposite the sources of the field-effect transistors to which they are connected, are connected to a source of reference potential.

Claim 21

A semiconductor image pick-up device according to claim 14, wherein each of said photodetectors comprises a phototransistor, the emitter of which is connected to the source of a respective field effect transistor, and the collector of which is connected to a source of reference potential.

Claim 22

A semiconductor image pick-up device according to claim 16, wherein each of said photodetectors and field-effect transistor is integrated in a common substrate.

Claim 23

A semiconductor image pick-up device according to claim 10, wherein each of said photodetectors and field-effect transistors are integrated in a common substrate.

Claim 24

A semiconductor image pick-up device according to claim 14, wherein each of said photodetectors and field-effect transistors are integrated in a common substrate.

Claim 25

A semiconductor image pick-up device comprising: first to n th photodetectors, where n is an integer greater than two; first to n th pairs of field-effect transistors, the sources of each transistor of each respective first to n th pair being connected to said first to n th photodetectors; a first output line which interconnects the drains of each respective one of the transistors of said first to n th pairs of field-effect transistors; a second output line which interconnects the drains of each respective other of the transistors of said first to n th pairs of field-effect transistors; a first address-pulse input line connected to the gate of the one transistor of said first pair of field-effect transistors; second to n th address-pulse input lines which interconnect the gates of each respective other transistor of said first to (n-1) th pairs of field-effect transistors and the gates of each respective one transistor of said second to n th pairs of field-effect transistors; an ( n + 1 ) th address pulse input line connected to the gate of the other transistors of said n th pair of field-effect transistors; a differential amplifier circuit connected to said first and second output lines; and circuit means for applying address-pulses sequentially to said first to ( n + 1 ) th input lines.

Claim 26

A semiconductor image pick-up device comprising: first to n th photodetectors, where n is an integer greater than two; first to n th pairs of field-effect transistors, the sources of each transistor of each respective first to n th pair being connected to said first to n th photodetectors; a first output line which interconnects the drains of each respective one of the transistors of said first to n th pairs of field-effect transistors; a second output line which interconnects the drains of each respective other of the transistors of said first to n th pairs of field-effect transistors; a first address-pulse input line connected to the gate of the one transistor of said first pair of field-effect transistors; second to n th address-pulse input lines which interconnect the gates of each respective other transistor of said first to (n-1) th pairs of field-effect transistors and the gates of each respective one transistor of said second to n th pairs of field-effect transistors; an ( n + 1 ) th address pulse input line connected to the gate of the other transistors of said n th pair of field-effect transistors; a differential amplifier circuit connected to said first and second output lines; and circuit means for applying address-pulses sequentially to said first to ( n + 1 ) th input lines.

Claim 27

A semiconductor image pick-up device according to claim 20, wherein said photodetectors comprise photodiodes the ends of which, opposite the sources of the field-effect transistors to which they are connected, are connected to a source of reference potential.

Claim 28

A semiconductor image pick-up device according to claim 20, wherein each of said photodetectors and field-effect transistors is integrated in a common substrate.

Claim 29

A semiconductor image pick-up device comprising: first and second photodetectors disposed adjacent each other; a first pair of field-effect transistors having their sources connected to said first photodetector and disposed to receive an optical information input; a second pair of field-effect transistors having their sources connected to said second photodetector and disposed to receive an optical information input; an auxiliary photodetector, disposed adjacent and first photodetector; an auxiliary field-effect transistor, having its source connected to said auxiliary photodetector and disposed to receive no optical information input; a first output line which interconnects the drains of one of the transistors of each of said first and second pairs of field-effect transistors; a second output line which interconnects the drains of the other of the transistors of each of said first and second pairs of field-effect transistors, and the drain of said auxiliary field-effect transistors; a first input line which interconnects the gate of said auxiliary field-effect transistor and the gate of the one transistor of said first pair of field-effect transistors; a second input line which interconnects the gate of the other transistor of said first pair of field-effect transistors and the gate of the one transistor of said second pair of field-effect transistors; first circuit means, connected to said first and second output lines, for generating a signal representative of the difference of the signals appearing on said first and second output lines; second circuit means, coupled to said first input line, for applying a first signal readout pulse to the gates of said auxiliary field-effect transistor and the one transistor of said first pair of field-effect transistors, so as to couple said first photodetector and said auxiliary photodetector to said first and second output lines, respectively, whereby said first circuit means will generate a signal representative of the difference of the signals corresponding to the outputs of said first photodetector and said auxiliary photodetector; and third circuit means, coupled to said second input line, for applying a second signal readout pulse, subsequent to said first signal readout pulse, to the gates of the other transistor of said first pair of field-effect transistors and the one transistor of said second pair of field-effect transistors, so as to couple said photodetector and said first photodetector to said first and second output lines, respectively, whereby said first circuit means will generate a signal representative of the difference of the signals corresponding to the outputs of said second photodetector and said first photodetector.

Claim 30

A semiconductor image pick-up device comprising: first and second photodetectors disposed adjacent each other; a first pair of field-effect transistors having their sources connected to said first photodetector and disposed to receive an optical information input; a second pair of field-effect transistors having their sources connected to said second photodetector and disposed to receive an optical information input; an auxiliary photodetector, disposed adjacent and first photodetector; an auxiliary field-effect transistor, having its source connected to said auxiliary photodetector and disposed to receive no optical information input; a first output line which interconnects the drains of one of the transistors of each of said first and second pairs of field-effect transistors; a second output line which interconnects the drains of the other of the transistors of each of said first and second pairs of field-effect transistors, and the drain of said auxiliary field-effect transistors; a first input line which interconnects the gate of said auxiliary field-effect transistor and the gate of the one transistor of said first pair of field-effect transistors; a second input line which interconnects the gate of the other transistor of said first pair of field-effect transistors and the gate of the one transistor of said second pair of field-effect transistors; first circuit means, connected to said first and second output lines, for generating a signal representative of the difference of the signals appearing on said first and second output lines; second circuit means, coupled to said first input line, for applying a first signal readout pulse to the gates of said auxiliary field-effect transistor and the one transistor of said first pair of field-effect transistors, so as to couple said first photodetector and said auxiliary photodetector to said first and second output lines, respectively, whereby said first circuit means will generate a signal representative of the difference of the signals corresponding to the outputs of said first photodetector and said auxiliary photodetector; and third circuit means, coupled to said second input line, for applying a second signal readout pulse, subsequent to said first signal readout pulse, to the gates of the other transistor of said first pair of field-effect transistors and the one transistor of said second pair of field-effect transistors, so as to couple said photodetector and said first photodetector to said first and second output lines, respectively, whereby said first circuit means will generate a signal representative of the difference of the signals corresponding to the outputs of said second photodetector and said first photodetector.