Patent US3945347A successfully refreshed from Google Patents.
← Back to Patent Explorer
US3945347A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making integrated circuits

Assignee: Panasonic Holdings Corp
•
Filing: 1973-10-16
•
Granted: 1976-03-23
•
Expires: 1993-10-16
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract In a method of making integrated circuits, prior to vapor deposition of metal layers on an insulating layer for interconnection, each opening on the insulating layer is filled with an embedded metal layer in order to smoothen the surface to be vapor deposited and to avoid undesirable thin parts of the vapor deposited metal layer at the step between the lower part in the opening and the elevated part on the insulating layer. The filling of the embedded metal layer in each opening is made by a first step of coating a metal layer on the whole surface of the principal face of the semi-conductor, which surface is coated by the insulating layer with specified openings and further by a photoresist layer which has been used for etching the insulating layer to form said openings and is left covering said insulating layer, and by the subsequent step of applying a photoresist removing liquid on the face to remove the photoresist layer and the part of metal layer still remaining on the photoresist layer.

Inventors

  • 👤 Toyoki Takemoto
  • 👤 Hiroshi Kuroda

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 15:53
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10W74/47; H10P; H10P76/00; H10P76/20; H10P76/202; H10W20/00; H10W20/40

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 221 words
Method of making an integrated circuit comprising the steps of: forming impurity diffused regions on the principal face of a semiconductor substrate, coating the principal face of said substrate with an insulating layer, coating said insulating layer with a photoresist layer of a specified pattern having openings on specified positions thereon, etching said insulating layer through said openings by utilizing said photoresist layer as an etching mask to form openings in said insulating layer from which specified regions of said principal face of the substrate are exposed, vapor depositing a metal layer of the thickness substantially equal to the thickness of the insulating layer over the entire principal face of said substrate, to fill said openings in the insulating layer through said insulating layer and said photoresist layer, applying a photoresist removing liquid to remove said photoresist layer and the part of said metal layer that is remaining on said photoresist layer while leaving only said metal layer in said openings at a level flush with the upper surface of said insulating layer, and forming on said insulating layer metal strips having widths substantially corresponding to said openings and overlying said openings to thereby contact said metal layer formed in said openings and embed the metal layer in the openings between said specified regions of the substrate and said metal strips.
Claim 2
Dependent Claim 221 words
Method of making an integrated circuit comprising the steps of: forming impurity diffused regions on the principal face of a semiconductor substrate, coating the principal face of said substrate with an insulating layer, coating said insulating layer with a photoresist layer of a specified pattern having openings on specified positions thereon, etching said insulating layer through said openings by utilizing said photoresist layer as an etching mask to form openings in said insulating layer from which specified regions of said principal face of the substrate are exposed, vapor depositing a metal layer of the thickness substantially equal to the thickness of the insulating layer over the entire principal face of said substrate, to fill said openings in the insulating layer through said insulating layer and said photoresist layer, applying a photoresist removing liquid to remove said photoresist layer and the part of said metal layer that is remaining on said photoresist layer while leaving only said metal layer in said openings at a level flush with the upper surface of said insulating layer, and forming on said insulating layer metal strips having widths substantially corresponding to said openings and overlying said openings to thereby contact said metal layer formed in said openings and embed the metal layer in the openings between said specified regions of the substrate and said metal strips.
Claim 3
Dependent Claim 14 words
A method according to claim 1 wherein the semicondutor substrate is formed of silicon.
Claim 4
Dependent Claim 15 words
A method according to claim 1 wherein the insulating layer is formed of silicon dioxide.
Claim 5
Dependent Claim 15 words
A method according to claim 1 wherein the integrated circuit is a metal-oxide-semiconductor integrated circuit.
Claim 6
Dependent Claim 16 words
A method according to claim 1 wherein the vapor deposited metal layers are formed of aluminum.
Claim 7
Dependent Claim 21 words
A method according to claim 1 wherein said impurity diffused regions are formed as parallel spaced strips on said principal face.
Claim 8
Dependent Claim 22 words
A method according to claim 6 wherein said metal strips are provided in spaced parallel disposition transversely to said impurity diffused regions.

References Cited (Backward Citations)

US3138744A Cited
US3160534A Cited
US3266127A Cited
US3498833A Cited
US3840982A Cited
US3747200A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-03-23 1979-09-22 1980-03-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-03-23 1983-09-22 1984-03-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-03-23 1987-09-22 1988-03-23 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag