Patent US3945194A successfully refreshed from Google Patents.
US3945194A
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Electronic quartz clock with integrated circuits
Assignee: ITT Inc
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Filing: 1974-12-05
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Granted: 1976-03-23
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Expires: 1994-12-05
Abstract
Abstract This relates to a quartz clock having a frequency divider IC with an adjustable and programmable dividing factor. The adjustable dividing factor is reached by suppression of the pulses to be divided in such a manner that the distribution of the suppressed pulses is optimized.
Inventors
- 👤 Wolfgang Gollinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:18
CPC Classifications
G; G04; G04G; G04G3/00; G04G3/02; G04G3/022; H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/662
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
159 words
In an electronic quartz clock, a frequency divider integrated circuit having an adjustable and programmable dividing factor comprising: means for providing a negative voltage; a crystal oscillator; an asynchronous frequency divider having a predetermined number of stages; a blanking circuit coupled between a first predetermined number of divider stages and a second predetermined number of divider stages; a switch coupled between said second predetermined number of stages and a third predetermined number of stages such that a portion of said second predetermined number of stages can be cut out of said frequency divider; an adjustment circuit for generating a number of control signals, said number being equal to said third predetermined number; and multiple gate logic means having as inputs said control signals and the outputs of said third predetermined number of stages, said logic means having an output coupled to said blanking circuit for suppressing a number of pulses generated by said oscillator in an evenly distributed manner.
Claim 2
Dependent Claim
159 words
In an electronic quartz clock, a frequency divider integrated circuit having an adjustable and programmable dividing factor comprising: means for providing a negative voltage; a crystal oscillator; an asynchronous frequency divider having a predetermined number of stages; a blanking circuit coupled between a first predetermined number of divider stages and a second predetermined number of divider stages; a switch coupled between said second predetermined number of stages and a third predetermined number of stages such that a portion of said second predetermined number of stages can be cut out of said frequency divider; an adjustment circuit for generating a number of control signals, said number being equal to said third predetermined number; and multiple gate logic means having as inputs said control signals and the outputs of said third predetermined number of stages, said logic means having an output coupled to said blanking circuit for suppressing a number of pulses generated by said oscillator in an evenly distributed manner.
Claim 3
Dependent Claim
46 words
A frequency divider according to claim 1 wherein said adjustment circuit contains for each input of said multiple gate logic means a transistor having a source coupled to ground, a gate coupled to said means for providing, and a drain coupled to a corresponding adjusting input.
References Cited (Backward Citations)
US3777471A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-23 | 1979-09-22 | 1980-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-23 | 1983-09-22 | 1984-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-23 | 1987-09-22 | 1988-03-23 | $7700.00 | Window Closed / Lapsed |