Semiconductor memory employing charge-coupled shift registers with multiplexed refresh amplifiers

Claim 2

A charge-coupled memory comprising: a plurality of charge-coupled shift registers, each of said shift registers including a first pair of channels and a second pair of channels, each of said channels being defined by a first region and a second region; a plurality of refresh means each for receiving an output charge from said second regions of said first pair of channels and for providing a refreshed charge to said second regions of said second pair of channels, and for receiving an output charge from said first regions of said second pair of channels and for providing a refreshed charge to said first regions of said first pair of channels; multiplexing means for multiplexing charge between said refresh means and said second regions of said first pair of channels and said second pair of channels, and for multiplexing charge between said refresh means and said first regions of said second pair of channels and said first pair of channels; and phased signal means for shifting charge in said shift registers coupled to said shift registers; whereby information may be stored and refreshed in said shift registers.

Claim 3

The memory defined in claim 1 wherein said phased signal means provides phased signals for shifting charge in each of said registers from said first regions of said first pair of channels, to said second regions of said first pair of channels, and from said second regions of said second pair of channels to said first regions of said second pair of channels.

Claim 4

The memory defined in claim 2 wherein said channels are in juxtaposition.

Claim 5

The memory defined by claim 3 wherein each of said registers include a plurality of gates for receiving said phased signals from said phased signal means, certain ones of said gates being operable both for shifting said charge and for multiplexing said charge.

Claim 6

The memory defined in claim 4 wherein said gates of each of said registers are disposed either on a first level above said channels, or on a second level above said channels.

Claim 7

The memory defined in claim 5 wherein said channels are n-channels.

Claim 8

In a charge-coupled memory, the combination of: a charge-coupled shift register having a first, second, third and fourth parallel channel, each channel having a first and a second end; a first and a second refresh amplifier, said first refresh amplifier being disposed adjacent to said first end of said parallel channels, and said second refresh amplifier being disposed adjacent to said second end of said parallel channels; multiplexing means for multiplexing charge between said first refresh amplifier and said first end of said first, second, third and fourth parallel channels, and for multiplexing charge between said second refresh amplifier and said second end of said first, second, third and fourth parallel channels; phased signal means for shifting charge in said first and second channels in one direction, and for shifting charge in said third and fourth channels in an opposite direction; whereby said parallel channels operate as a recirculating shift register in a memory.

Claim 9

In a charge-coupled memory, the combination of: a charge-coupled shift register having a first, second, third and fourth parallel channel, each channel having a first and a second end; a first and a second refresh amplifier, said first refresh amplifier being disposed adjacent to said first end of said parallel channels, and said second refresh amplifier being disposed adjacent to said second end of said parallel channels; multiplexing means for multiplexing charge between said first refresh amplifier and said first end of said first, second, third and fourth parallel channels, and for multiplexing charge between said second refresh amplifier and said second end of said first, second, third and fourth parallel channels; phased signal means for shifting charge in said first and second channels in one direction, and for shifting charge in said third and fourth channels in an opposite direction; whereby said parallel channels operate as a recirculating shift register in a memory.

Claim 10

The memory defined by claim 7 wherein said second refresh amplifier receives charge from said second end of said first and second channels and provides a refreshed charge to said second ends of said third and fourth channels, and wherein said first refresh amplifier receives charge from said first end of said third and fourth channels and provides a refreshed charge to said first ends of said first and second channels.

Claim 11

The memory defined by claim 8 wherein said refreshed charge provided by said first and said second amplifier represents the opposite binary state from the charge received by said first and said second amplifier.

Claim 12

A recirculating charge-coupled shift register comprising: a first and a second adjacent regions; a third and a fourth adjacent regions, said first and third regions defining a first channel and said second and fourth regions defining a second channel parallel to said first channel; a fifth and a sixth adjacent region; a seventh and an eighth adjacent region, said fifth and seventh regions defining a third channel and said sixth and eighth regions defining a fourth channel parallel to said first, second, third and fourth channels; a first refresh circuit for refreshing charge having an input coupled to said first and second regions and an output coupled to said seventh and eighth regions; a second refresh circuit for refreshing charge having an input coupled to said fifth and sixth regions and an output coupled to said third and fourth regions; multiplexing means for multiplexing charge between said first refresh circuit and the output of said first and second region and the input of said seventh and eighth regions and for multiplexing charge between said second refresh circuit and the output of said fifth and sixth regions and the input of said third and fourth regions; phased signal means for shifting charge in said first and second channels in one direction, and for shifting charge in said third and fourth channels in an opposite direction; whereby charge may be circulated in said first, second, third and fourth regions.

Claim 13

A recirculating charge-coupled shift register comprising: a first and a second adjacent regions; a third and a fourth adjacent regions, said first and third regions defining a first channel and said second and fourth regions defining a second channel parallel to said first channel; a fifth and a sixth adjacent region; a seventh and an eighth adjacent region, said fifth and seventh regions defining a third channel and said sixth and eighth regions defining a fourth channel parallel to said first, second, third and fourth channels; a first refresh circuit for refreshing charge having an input coupled to said first and second regions and an output coupled to said seventh and eighth regions; a second refresh circuit for refreshing charge having an input coupled to said fifth and sixth regions and an output coupled to said third and fourth regions; multiplexing means for multiplexing charge between said first refresh circuit and the output of said first and second region and the input of said seventh and eighth regions and for multiplexing charge between said second refresh circuit and the output of said fifth and sixth regions and the input of said third and fourth regions; phased signal means for shifting charge in said first and second channels in one direction, and for shifting charge in said third and fourth channels in an opposite direction; whereby charge may be circulated in said first, second, third and fourth regions.

Claim 14

The recirculating charge-coupled shift register defined in claim 10 wherein said first, second, third, fourth, fifth, sixth, seventh and eighth regions and said first and second refresh circuits are disposed on a common silicon substrate.

Claim 15

The recirculating shift register defined in claim 11 including a plurality of first level gates disposed at a first level above said first, second, third and fourth channels and a plurality of second level gates disposed at a second level above said first, second, third and fourth channels.

Claim 16

The recirculating shift register defined by claim 12 wherein said first level gates and said second level gates are defined by generally parallel lines disposed transversely to said parallel channels.

Claim 17

The recirculating shift register defined in claim 13 wherein said first, second, third, fourth, fifth, sixth, seventh and eighth regions are n-type regions.

Claim 18

The recirculating shift register defined in claim 14 wherein said first and third regions are larger than said second and fourth regions.

Claim 19

The recirculating shift register defined in claim 15 including signal means for shifting charge along said first and second channels in one direction and along said third and fourth channels in the opposite direction.

Claim 20

The recirculating shift register defined in claim 16 wherein said generally parallel lines defining gates at one of said first or second levels crossover said generally parallel lines defining gates at the other of said first or second levels between said second and third channels.