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US3943555A Expired / Lapsed US ⏱️ 0.0 years remaining

SOS Bipolar transistor

Assignee: RCA Corp
•
Filing: 1974-05-02
•
Granted: 1976-03-09
•
Expires: 1994-05-02
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Abstract

Abstract A planar bipolar transistor is made by the successive ion implantations of selected atoms into selected regions of a layer of doped single-crystal silicon on an insulating substrate, such as sapphire or spinel. The silicon layer is epitaxially grown, has a thickness of between 0.5 and 5 μm, and is formed in two strata of different resistivities. A collector contact well is ion implanted into the upper stratum and annealed to diffuse it into the lower stratum of lower resistivity. The transistor is isolated, as a mesa, on the substrate; and an edge-guard region is ion implanted through the periphery of the mesa, except in the region of the emitter-base junction.

Inventors

  • 👤 Charles William Mueller
  • 👤 Edward Curtis Douglas

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 20:17
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/03; H10D99/00; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10W10/021; H10W10/20

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 146 words
A bipolar transistor comprising: an electrically insulating substrate, a mesa comprising a layer of single-crystal semiconductor material of one type conductivity on a surface of said substrate, said layer having a planar surface and a thickness of between about 0.5 μm and about 5 μm, a base region of an opposite type conductivity disposed in a portion of said layer, said layer comprising a collector region, an emitter region of said one type conductivity disposed in a portion of said base region and defining with said base region an emitter-base junction, each of said regions having a planar surface coplanar with said planar surface of said layer, said mesa having a periphery in which a portion of said emitter-base junction terminates, and an edge-guard region of said one type conductivity disposed in said periphery of said mesa, except in said emitter region and said emitter-base junction.
Claim 2
Dependent Claim 146 words
A bipolar transistor comprising: an electrically insulating substrate, a mesa comprising a layer of single-crystal semiconductor material of one type conductivity on a surface of said substrate, said layer having a planar surface and a thickness of between about 0.5 μm and about 5 μm, a base region of an opposite type conductivity disposed in a portion of said layer, said layer comprising a collector region, an emitter region of said one type conductivity disposed in a portion of said base region and defining with said base region an emitter-base junction, each of said regions having a planar surface coplanar with said planar surface of said layer, said mesa having a periphery in which a portion of said emitter-base junction terminates, and an edge-guard region of said one type conductivity disposed in said periphery of said mesa, except in said emitter region and said emitter-base junction.
Claim 3
Dependent Claim 29 words
A bipolar transistor as described in claim 1, wherein: said substrate is an electrical insulator selected from the group consisting of sapphire and spinel, and said layer comprises silicon.
Claim 4
Dependent Claim 80 words
A bipolar transistor as described in claim 1, wherein: an elongated collector contact well is disposed in said layer, an elongated base contact well is disposed in said base region, said emitter region and is elongated and parallel to both said collector contact well and said base contact well, whereby said transistor can be etched in portions transversely disposed to said emitter region so as to divide said transistor into a plurality of mesas, each mesa comprising a bipolar transistor.

References Cited (Backward Citations)

US3383567A Cited
US3486892A Cited
US3602781A Cited
US3567508A Cited
US3666548A Cited
US3761319A Cited
US3660732A Cited
US3890632A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-03-09 1979-09-08 1980-03-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-03-09 1983-09-08 1984-03-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-03-09 1987-09-08 1988-03-09 $7700.00 Window Closed / Lapsed

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