Device for preventing drunken driving of vehicle

Claim 2

A vehicle operation inhibitor control system for a vehicle having an engine, an electric power source and an electric system for controlling the engine operation when energized by said electric power source, wherein said inhibitor control system comprises: connect means for connecting said electric power source to said electric system when said connect means is energized; a display having a single screen for displaying a character on the single screen in response to a character signal applied thereto when said display is triggered by an external trigger signal; control means for consecutively applying a first group of character signals respectively representing a first group of characters different from one another to said display while applying a trigger signal to said display during a first time period, and applying to said display a second group of character signals respectively representing a second group of characters including at least one character in addition to said first group of characters during a second time period later than said first period; and detect means operable by the vehicle operator for energizing said connect means at each time when one character of said first group is displayed by said display during said second period.

Claim 3

A vehicle operation inhibitor control system according to claim 1, in which said display includes means for receiving a plurality of input signals and means for receiving an external trigger signal to display a character on the screen according to a character signal applied thereto when it receives an external trigger pulse signal.

Claim 4

A vehicle operation inhibitor control system according to claim 2, in which said control means includes a multi-stage ring counter having a corresponding by-pass circuit cooperative with each stage thereof for by-passing a stage when the corresponding by-pass circuit is energized, a set terminal at several stages thereof and a trigger terminal common to all of the stages; means for applying the output of said ring counter to said means for receiving input signals of said display; a high frequency trigger pulse generator for producing a high frequency trigger pulse train; a low frequency trigger pulse generator for producing a low frequency trigger pulse train; a first gate pulse generator for producing a first gate pulse having a duration of said first period; a second gate pulse generator for producing a second gate pulse having a duration of said second period; memory means for memorizing therein the characters displayed by said display and energizing selected ones of the by-pass circuits according to the memorized characters; set means for applying a logic 1 level signal to one of said set terminals at the beginning of each low frequency trigger pulse; display actuating means for applying the inverse of said low frequency trigger pulse train to said means for receiving a trigger signal of the display when the actuating means is energized by said first gate pulse and for applying said second gate pulse to said means for receiving a trigger signal of the display; ring counter trigger means for applying said high frequency pulse train modulated by said low frequency pulse train to said trigger terminal of said ring counter when the ring counter trigger means is energized by said first gate pulse and for applying said low frequency pulse train to said trigger terminal of the ring counter when it is energized by said second gate pulse.

Claim 5

A vehicle operation inhibitor control system according to claim 3, in which said low frequency trigger pulse generator is a astable multi-vibrator.

Claim 6

A vehicle operation inhibitor control system according to claim 3, in which said high frequency trigger pulse generator is a astable multivibrator for developing an oscillatory output signal when enegized; and said ring counter trigger means includes a first AND gate receptive of said low frequency trigger pulse train and said first gate pulse, a monostable multivibrator receptive of the first AND gate output for producing a short pulse when it is energized by each of the low frequency trigger pulses passed by said first AND gate; an inverter for inverting the output of said monostable multivibrator; a second AND gate receptive of the inverter output of said monostable multivibrator and the low frequency trigger pulse train passed through said first AND gate for applying an output to said astable maultivibrator; a third AND gate receptive of said low frequency trigger pulse train and said second gate pulse, and an OR gate receptive of the output signal from said third AND gate and said astable multivibrator for applying an output to the trigger terminal of the ring counter.

Claim 7

A vehicle operation inhibtior control system according to claim 3, in which said memory means includes pulse generating means responsive to the low frequency trigger pulses for producing a memory pulse at the trailing portion of each low frequency trigger pulse; a number of flip-flop circuits equal to the number of stages of said ring counter; a plurality of AND gates each corresponding to one of said flip-flop circuits for connecting the output terminal of the corresponding stage of said ring counter to the set terminal of the corresponding flip-flop circuit when triggered by a memory pulse; and means for applying the memory pulses to the plurality of AND gates.

Claim 8

A vehicle operation inhibitor control system according to claim 6, in which said detect means includes a plurality of AND gate each corresponding to one of said flip-flop circuits for connecting the trigger terminal of said flip-flop circuit to the output of the corresponding stage of said ring counter when triggered by said second gate pulse; means for applying said second gate pulse to said plurality of AND gates included in said detect means; a pulse generator manually operable for producing a pulse and for applying said pulse to J and K terminals of all of said flip-flop circuits, and means for energizing said connect means when said flip-flop circuits are all reset by the pulse.