US3939304A
Expired / Lapsed
US
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Decommutator for extracting zero and one bits from a coded message of duration-modulated pulses
Assignee: Centre National d'Études Spatiales
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Filing: 1975-01-30
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Granted: 1976-02-17
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Expires: 1995-01-30
Abstract
Abstract Decommutator operating on a coded message formed of duration-modulated pulse trains, whereby extraction of the logic signal corresponding to an information is effected by comparing the pulse integrated over the information-characterizing portion of its duration with a reference quantity obtained locally by integrating the pulse over a portion of its duration not characterizing said information, this comparison having for effect to establish the reference voltage threshold of a synchronizing bit that identifies the latter.
Inventors
- 👤 Andre Auguste Ribes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:32
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/06; G; G08; G08C; G08C19/00; G08C19/16; G08C19/22
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
278 words
A decommutator for extracting 0 and 1 bits from duration-modulated pulses of a conventionally coded message in which the initial instants of the pulses are evenly spaced over a time period T and the length of which varies according to the information contained in the pulse, said pulses being first detected before being applied to the decommutator, said decommutator comprising a first integrator and a second integrator, means for applying the detected duration-modulated pulses conjointly to both said integrators, a gated storage element, a multiplying member having a constant multiplication factor, means for connecting the first integrator to the storage element so as to store therein the signals integrated by this first integrator, means for connecting the second integrator to the multiplying member so as to multiply the magnitude of the signals integrated in said second integrator by said constant factor, a comparison means having two inlets and one outlet, means for connecting the storage element and the multiplying member each to one different inlet of the comparison means, and means for controlling the integration intervals of the integrators and the gating of the storage element so that a said pulse is integrated in the first integrator over a period carrying no said information and stored in a succeeding portion of the same period and that said pulse is integrated in the second intergrator over a period carrying said information and multiplied by said factor, whereby the stored integrated signals and the multiplied integrated signals are compared in said comparison means for providing 0 and 1 bits, and means for connecting the outlet of said comparison means to a bit detector for detecting said 0 and 1 bits.
Claim 2
Dependent Claim
278 words
A decommutator for extracting 0 and 1 bits from duration-modulated pulses of a conventionally coded message in which the initial instants of the pulses are evenly spaced over a time period T and the length of which varies according to the information contained in the pulse, said pulses being first detected before being applied to the decommutator, said decommutator comprising a first integrator and a second integrator, means for applying the detected duration-modulated pulses conjointly to both said integrators, a gated storage element, a multiplying member having a constant multiplication factor, means for connecting the first integrator to the storage element so as to store therein the signals integrated by this first integrator, means for connecting the second integrator to the multiplying member so as to multiply the magnitude of the signals integrated in said second integrator by said constant factor, a comparison means having two inlets and one outlet, means for connecting the storage element and the multiplying member each to one different inlet of the comparison means, and means for controlling the integration intervals of the integrators and the gating of the storage element so that a said pulse is integrated in the first integrator over a period carrying no said information and stored in a succeeding portion of the same period and that said pulse is integrated in the second intergrator over a period carrying said information and multiplied by said factor, whereby the stored integrated signals and the multiplied integrated signals are compared in said comparison means for providing 0 and 1 bits, and means for connecting the outlet of said comparison means to a bit detector for detecting said 0 and 1 bits.
Claim 3
Dependent Claim
67 words
A decommutator according to claim 1 for extracting the 0 and 1 bits from a message of the TDCS type, wherein in the period T the first integrator integrates in the time interval O - T/4, the second integrator integrates in the time interval T/4 - T/2 and the storage element stores in the time interval T/4 - T/2 and wherein said multiplying element is a doubler.
Claim 4
Dependent Claim
35 words
A decommutator according to claim 1, wherein the first integrator, the gated storage element and the means for connecting the first integrator to the storage element are embodied in one single integrating and storing member.
Claim 5
Dependent Claim
34 words
A decommutator according to claim 1, wherein the second integrator, the multiplying member and the means for connecting the second integrator to the multiplying member are embodied in one single integrating and multiplying member.
Claim 6
Dependent Claim
217 words
A decommutator according to claim 1 for extracting the 0 and 1 bits and the synchronizing pulses from a message of the TDCS type, wherein in the period T the first integrator integrates in the time interval .-T/4, the storage element stores in the time interval T/4 - 3T/4 and the second integrator integrates in the time interval T/4 - T/2 and wherein said multiplying element is a doubler, said decommutator also comprising a third integrator, a supplemental doubler and supplemental comparision means having two inlets and one outlet, means for applying the detected duration-modulated pulses to the third integrator conjointly with the other two integrators, means for controlling the integration of said third integrator in the time interval T/2 - 3T/4, said means for controlling being the same means for controlling the integrating intervals of the first and second integrators; means for connecting the third integrator to the supplemental doubler so as to double the magnitude of the signals integrated in said third integrator, means for connecting the storage element and the supplemental doubler each to one different inlet of the supplemental comparison means, for providing said synchronizing pulses at the outlet of said supplemental comparison means, while the voltage at the outlet of the first mentioned comparison means corresponds to the 0 and 1 bits.
Claim 7
Dependent Claim
89 words
A decommutator according to claim 5, wherein the first integrator, the gated storage element and the means for connecting the first integrator to the storage element are embodied in an integrating and storing member, the second integrator, the multiplying member and the means for connecting the second integrator to the doubling member are embodied in a first integrating and doubling member, and the third integrator, the supplemental doubler and the means for connecting the third integrator to the supplemental doubler are embodied in a second integrating and doubling member.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-02-16 | 1979-08-18 | 1980-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-02-16 | 1983-08-18 | 1984-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-02-16 | 1987-08-18 | 1988-02-17 | $7700.00 | Window Closed / Lapsed |