Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
127 words
A timing ramp generating comprising first and second transistors each having collector, emitter and base electrodes, a capacitor connected between base of said first transistor and the collector of said second transistor, a resistance connected between the base and emitter of said first transistor, the emitter of said first transistor being connected to a first terminal and the base of said second transistor, a resistive load coupled intermediate the collector of said second transistor, and a second terminal, said second terminal connected to the collector of said first transistor, source of d.c. voltage connected across said first and second terminals, whereby a constant current charges the capacitor and a linear timing ramp is generated at the collector of said second transistor which approaches the applied d.c. voltage.
Claim 2
Dependent Claim
127 words
A timing ramp generating comprising first and second transistors each having collector, emitter and base electrodes, a capacitor connected between base of said first transistor and the collector of said second transistor, a resistance connected between the base and emitter of said first transistor, the emitter of said first transistor being connected to a first terminal and the base of said second transistor, a resistive load coupled intermediate the collector of said second transistor, and a second terminal, said second terminal connected to the collector of said first transistor, source of d.c. voltage connected across said first and second terminals, whereby a constant current charges the capacitor and a linear timing ramp is generated at the collector of said second transistor which approaches the applied d.c. voltage.
Claim 3
Dependent Claim
179 words
A timing ramp generator including a main transistor having collector, emitter and base electrodes and having a capacitor connected between collector and base, a resistance connected between base and emitter, the emitter being connected directly to a first terminal, a resistive load in the collector circuit, means for supplying a d.c. voltage across a second input terminal in the collector circuit and the first terminal to switch on the transistor when said voltage is supplied, and to operate in the region where the base-emitter potential is substantially constant, thus providing a constant current to charge the capacitor and thereby obtaining a linear timing ramp at the collector which approaches the potential of said signal, a constant current device in the collector circuit of said main transistor, said constant current device includes a second transistor of opposite conductivity type to said main transistor, said second transistor havings its base connected to a reference potential, the collector-emitter circuit of said second transistor being connected in series with the collector emitter circuit of said main transistor across said first and second terminals.
Claim 4
Dependent Claim
179 words
A timing ramp generator including a main transistor having collector, emitter and base electrodes and having a capacitor connected between collector and base, a resistance connected between base and emitter, the emitter being connected directly to a first terminal, a resistive load in the collector circuit, means for supplying a d.c. voltage across a second input terminal in the collector circuit and the first terminal to switch on the transistor when said voltage is supplied, and to operate in the region where the base-emitter potential is substantially constant, thus providing a constant current to charge the capacitor and thereby obtaining a linear timing ramp at the collector which approaches the potential of said signal, a constant current device in the collector circuit of said main transistor, said constant current device includes a second transistor of opposite conductivity type to said main transistor, said second transistor havings its base connected to a reference potential, the collector-emitter circuit of said second transistor being connected in series with the collector emitter circuit of said main transistor across said first and second terminals.