Offset voltage correction circuit for multiple video channel imager

Claim 2

An imaging system comprising a. a two-dimensional array of sensing sites of MIS cell pairs, said sensing sites being arranged in a matrix of rows and columns; b. a plurality of column lines, each connected respectively to the sensing sites of each column, said lines arranged in a plurality of consecutively numbered sets, each set including the same number of consecutively numbered lines; c. a plurality of charge integrating means connected to one of said lines of each set, respectively, for simultaneous readout of charges through the lines of at least one said set; d. switch means for connecting each said set, in turn, for readout; e. a plurality of video channel circuits, respectively, in circuit with each said integrating means for respectively transmitting an output signal from each said integrating means; and f. a correction circuit means in circuit with said plurality of video channel circuit means for generating a correction signal to cancel a D.C. offset voltage between the output signals on said video channel circuit means.

Claim 3

The system of claim 1 further comprising multiplexing means connected between said plurality of video channel circuit means and said correction circuit means for multiplexing said outputs to provide a composite video signal.

Claim 4

The system of claim 2 further comprising signal adding means having a first input connected to the output of said multiplexing means and a second input connected to the output of said correction circuit means.

Claim 5

The system of claim 1 wherein said correction circuit means further comprises differential integrating means for integrating said offset voltage to generate an output signal substantially corresponding to the difference between an average of the outputs of the cell pairs of the odd numbered columns and an average of the outputs of the cell pairs of the even numbered columns.

Claim 6

The system of claim 4 wherein said correction circuit means further comprises an odd sampling circuit means for providing a continuous time variable signal corresponding to the outputs of the cell pairs on said odd numbered column lines, said odd sampling circuit signal providing a first input to said differential integrating means and an even sampling circuit means for providing a continuous time variable signal corresponding to the outputs of the cell pairs on said even numbered column lines, said even sampling circuit signal providing a second input to said differential integrating means.

Claim 7

The system of claim 5 wherein said correction circuit further comprises a modulator means connected to said differential integrating means for modulating the output of said differential integrating means to generate said correction signal, said correction signal being comprised of a square wave opposite in phase and equal in period to the composite video output.

Claim 8

The system of claim 6 further comprising multiplexing means connected between said plurality of video channel circuit means and said correction circuit means for multiplexing said video channel outputs to provide a composite video signal.

Claim 9

The system of claim 7 further comprising signal adding means having a first input connected to the output of said multiplexing means and a second input connected to the output of said modulator means.

Claim 10

An imaging system comprising a. a semiconductor substrate having a major surface; b. a first and a second plurality of conductive plates, each overlying and in an insulated relationship to said major surface thereby to form first and second pluralities of MIS capacitors, respectively, each of said first MIS capacitors being adjavent and coupled to a respective one of said second MIS capacitors to form a plurality of pairs of MIS capacitors, said pairs arranged in a matrix of rows and columns; c. a plurality of column conductor lines arranged in plurality of consecutively numbered sets, each set having an equal number of consecutively numbered lines, each line connected to the second plates of each column, respectively; d. a plurality of column switches; e. a plurality of consecutively numbered terminals equal in number to the number of sets, each line connected through a respective one of said column switches to the terminal corresponding in number to the set number of said line; f. a plurality of row conductor lines, each row line connected to said first plates of each row, respectively; g. a first voltage means for providing a first voltage between said row conductor lines and said substrate to deplete respective first portions of said substrate lying thereunder of majority charge carriers; h. a second voltage means connected in circuit between each set of said column conductor lines and said substrate for providing a second voltage between said column conductor lines and said substrate to deplete respective second portions of said substrate lying thereunder of majority charge carriers, said substrate maintained at a fixed potential in relation to said second voltage means; i. means for exposing said substrate to radiation whereby charge is stored in said first and second portions of said substrate; j. first means for collapsing and reestablishing said first voltage on each of said row conductor lines in sequence during a respective period of time; k. means for actuating the column switches of each set during a respective second period of time whereby the column lines of each set are connected in turn to said terminals; l. a plurality of circuit means each connected between a respective one of said terminals and said second voltage means; m. second means for collapsing and reestablishing said second voltage on said terminals during said second periods of time, whereby charge stored in the second semiconductor capacitors of each set is simultaneously driven out of said respective second capacitors and currents are caused to flow simultaneously in each of said circuit means; n. each of said circuit means including means for integrating each of said current flows with respect to time to provide a respective output of sequentially occurring levels of voltage; o. a plurality video channel circuit means each connected to respective ones of said integrating means for providing a plurality of video channel outputs; p. correction circuit means, connected to said plurality of video channel circuit means for generating a correction signal to cancel a D.C. offset voltage between said video channel outputs.

Claim 11

An imaging system comprising a. a semiconductor substrate having a major surface; b. a first and a second plurality of conductive plates, each overlying and in an insulated relationship to said major surface thereby to form first and second pluralities of MIS capacitors, respectively, each of said first MIS capacitors being adjavent and coupled to a respective one of said second MIS capacitors to form a plurality of pairs of MIS capacitors, said pairs arranged in a matrix of rows and columns; c. a plurality of column conductor lines arranged in plurality of consecutively numbered sets, each set having an equal number of consecutively numbered lines, each line connected to the second plates of each column, respectively; d. a plurality of column switches; e. a plurality of consecutively numbered terminals equal in number to the number of sets, each line connected through a respective one of said column switches to the terminal corresponding in number to the set number of said line; f. a plurality of row conductor lines, each row line connected to said first plates of each row, respectively; g. a first voltage means for providing a first voltage between said row conductor lines and said substrate to deplete respective first portions of said substrate lying thereunder of majority charge carriers; h. a second voltage means connected in circuit between each set of said column conductor lines and said substrate for providing a second voltage between said column conductor lines and said substrate to deplete respective second portions of said substrate lying thereunder of majority charge carriers, said substrate maintained at a fixed potential in relation to said second voltage means; i. means for exposing said substrate to radiation whereby charge is stored in said first and second portions of said substrate; j. first means for collapsing and reestablishing said first voltage on each of said row conductor lines in sequence during a respective period of time; k. means for actuating the column switches of each set during a respective second period of time whereby the column lines of each set are connected in turn to said terminals; l. a plurality of circuit means each connected between a respective one of said terminals and said second voltage means; m. second means for collapsing and reestablishing said second voltage on said terminals during said second periods of time, whereby charge stored in the second semiconductor capacitors of each set is simultaneously driven out of said respective second capacitors and currents are caused to flow simultaneously in each of said circuit means; n. each of said circuit means including means for integrating each of said current flows with respect to time to provide a respective output of sequentially occurring levels of voltage; o. a plurality video channel circuit means each connected to respective ones of said integrating means for providing a plurality of video channel outputs; p. correction circuit means, connected to said plurality of video channel circuit means for generating a correction signal to cancel a D.C. offset voltage between said video channel outputs.

Claim 12

The system of claim 9 further comprising multiplexing means connected between said plurality of video channel circuit means and said correction circuit means for multiplexing said outputs to provide a composite video signal.

Claim 13

The system of claim 10 further comprising signal adding means having a first input connected to the output of said multiplexing means and a second input connected to the output of said correction circuit means.

Claim 14

The system of claim 9 wherein said correction circuit means further comprises differential integrating means for integrating said offset voltage to generate an output signal substantially corresponding to the difference between an average of the outputs of the cell pairs of the odd numbered columns and an average of the outputs of the cell pairs of the even numbered columns.

Claim 15

The system of claim 12 wherein said correction circuit means further comprises an odd sampling circuit means for providing a continuous time variable signal corresponding to the outputs of the cell pairs on said odd numbered column lines, said odd sampling circuit signal providing a first input to said differential integrating means and an even sampling circuit means for providing a continuous time variable signal corresponding to the outputs of the cell pairs on said even numbered column lines, said even sampling circuit signal providing a second input to said differential integrating means.

Claim 16

The system of claim 13 wherein said correction circuit further comprises a modulator means connected to said differential integrating means for modulating the output of said differential integrating means to generate said correction signal, said correction signal being comprised of a square wave opposite in phase and equal in period to the composite video output.

Claim 17

The system of claim 14 further comprising multiplexing means connected between said plurality of video channel circuit means and said correction circuit means for multiplexing said video channel outputs to provide a composite video signal.

Claim 18

The system of claim 15 further comprising signal adding means having a first input connected to the output of said multiplexing means and a second input connected to the output of said modulator means.