Patent US3936857A successfully refreshed from Google Patents.
US3936857A
Expired / Lapsed
US
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Insulated gate field effect transistor having high transconductance
Assignee: NEC Corp
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Filing: 1974-06-28
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Granted: 1976-02-03
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Expires: 1994-06-28
Abstract
Abstract An insulated gate field effect transistor having improved high-frequency operating characteristics includes an extended region electrically connected to one of the source and drain regions and spaced from the surface of the substrate. The extended region extends toward the other of the source and drain regions such that the distance between the source and drain regions is relatively small within the substrate and relatively large at the surface of the substrate.
Inventors
- 👤 Michihiro Ota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:17
CPC Classifications
H; H10; H10D; H10D99/00; H10D30/00; H10D30/60; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/106; Y10S148/145
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
131 words
An insulated gate field effect transistor comprising a semiconductor substrate of one conductivity type, source and drain regions of the opposite conductivity type formed in said semiconductor substrate, at least one extended region of said opposite conductivity type electrically connected to and extending from one of said source and drain regions toward the other of said source and drain regions, said at least one extended region being formed within said semiconductor substrate and electrically isolated from the other of said source and drain regions by a gap, a gate insulation film formed on said surface of said semiconductor substrate between said source and drain regions, and a gate electrode formed on said gate insulation film, said gate electrode overlying said gap and overlapping at least a part of said extended region.
Claim 2
Dependent Claim
131 words
An insulated gate field effect transistor comprising a semiconductor substrate of one conductivity type, source and drain regions of the opposite conductivity type formed in said semiconductor substrate, at least one extended region of said opposite conductivity type electrically connected to and extending from one of said source and drain regions toward the other of said source and drain regions, said at least one extended region being formed within said semiconductor substrate and electrically isolated from the other of said source and drain regions by a gap, a gate insulation film formed on said surface of said semiconductor substrate between said source and drain regions, and a gate electrode formed on said gate insulation film, said gate electrode overlying said gap and overlapping at least a part of said extended region.
Claim 3
Dependent Claim
43 words
The field effect transistor of claim 1, in which first and second ones of said extended regions are electrically connected to said source and drain regions respectively and extend toward one another, a gap being defined by said first and second extended regions.
Claim 4
Dependent Claim
27 words
The field effect transistor of claim 1, in which said gate electrode is spaced inwardly from each of said source and drain regions and overlies said gap.
Claim 5
Dependent Claim
33 words
The field effect transistor of claim 3, in which the upper surfaces of said extended regions are located at a distance from said surface of said substrate of between 0.01 and 2.0 microns.
Claim 6
Dependent Claim
33 words
The field effect transistor of claim 3, in which the upper surfaces of said extended regions are located at a distance from said surface of said substrate of between 0.05 and 1.0 microns.
Claim 7
Dependent Claim
20 words
The field effect transistor of claim 4, in which the width of said gap is between 1 and 3 microns.
Claim 8
Dependent Claim
31 words
The field effect transistor of claim 1, in which said gate electrode overlies the area of said substrate between said extended region and the other of said source and drain regions.
Claim 9
Dependent Claim
29 words
The field effect transistor of claim 1, in which the impurity concentration of said semiconductor substrate is substantially uniform and between 10 14 and 10 16 /cm 3 .
References Cited (Backward Citations)
US3615934A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-02-02 | 1979-08-04 | 1980-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-02-02 | 1983-08-04 | 1984-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-02-02 | 1987-08-04 | 1988-02-03 | $7700.00 | Window Closed / Lapsed |