US3935476A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Combination output/input logic for integrated circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1974-12-13
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Granted: 1976-01-27
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Expires: 1994-12-13
Abstract
Abstract Method and circuit for both outputting and inputting data by way of a single pin connector for an integrated circuit chip is disclosed. Data from the chip is fed through an output buffer on the chip and a standard pin connector to external circuitry. The input and the output of the output buffer are connected to separate logic inputs of a comparator such as an EXCLUSIVE OR gate. For data output, the external circuitry allows the output buffer to follow the input of the buffer, in which case the output of the EXCLUSIVE OR gate is a logic 0. However, when the external circuitry overrides the output of the output buffer causing the output to be different from the input to the buffer, the output of the EXCLUSIVE OR gate produces a logic 1 signal which indicates that data is being input and that the data at the pin connector is valid input data.
Inventors
- 👤 Robert John Paluck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:52
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1731; H03K19/1732
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
135 words
In integrated logic circuits, the combination of: a data pin for transferring data between the integrated logic circuit and an external logic circuit; an output buffer having a logic input and a logic output, the logic output being connected to the data pin; comparator logic means having one logic input logically coupled to the logic input of the output buffer and another logic input logically coupled to the logic output of the output buffer, and a logic output for producing an "input enable" signal when the logic inputs are different whereby the logic output of the output buffer can be driven by an external circuit to a logic level different from that applied to the logic input of the output buffer to produce an input enable signal at the output of the comparator logic means.
Claim 2
Dependent Claim
135 words
In integrated logic circuits, the combination of: a data pin for transferring data between the integrated logic circuit and an external logic circuit; an output buffer having a logic input and a logic output, the logic output being connected to the data pin; comparator logic means having one logic input logically coupled to the logic input of the output buffer and another logic input logically coupled to the logic output of the output buffer, and a logic output for producing an "input enable" signal when the logic inputs are different whereby the logic output of the output buffer can be driven by an external circuit to a logic level different from that applied to the logic input of the output buffer to produce an input enable signal at the output of the comparator logic means.
Claim 3
Dependent Claim
34 words
The combination of claim 1 further characterized by circuitry external to the integrated logic circuit for overriding the logic level applied to the pin by the output buffer for inputting data to the circuit.
Claim 4
Dependent Claim
131 words
In an integrated logic circuit, the method of outputting and inputting logic data through a single connector pin which comprises: outputting data by passing output logic data through an output buffer to the connector pin, while logically detecting that the logic input to the data buffer is the same as the logic output applied to the pin; and inputting data to the integrated circuit by overriding the logic level which would otherwise be produced on the pin by the output buffer in response to a logic input to the buffer while logically detecting within the integrated circuit that the logic input to the output buffer and the logic level on the pin are different to produce a logic signal internally of the intergrated circuit indicating that the data is being input.
Claim 5
Dependent Claim
131 words
In an integrated logic circuit, the method of outputting and inputting logic data through a single connector pin which comprises: outputting data by passing output logic data through an output buffer to the connector pin, while logically detecting that the logic input to the data buffer is the same as the logic output applied to the pin; and inputting data to the integrated circuit by overriding the logic level which would otherwise be produced on the pin by the output buffer in response to a logic input to the buffer while logically detecting within the integrated circuit that the logic input to the output buffer and the logic level on the pin are different to produce a logic signal internally of the intergrated circuit indicating that the data is being input.
References Cited (Backward Citations)
US3573756A
Cited
US3699544A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-01-26 | 1979-07-28 | 1980-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-01-26 | 1983-07-28 | 1984-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-01-26 | 1987-07-28 | 1988-01-27 | $7700.00 | Window Closed / Lapsed |