Patent US3935387A successfully refreshed from Google Patents.
US3935387A
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Pulse generator for television for generating at least one pulse series having pulses of different duration and repetition period
Assignee: US Philips Corp
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Filing: 1973-01-02
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Granted: 1976-01-27
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Expires: 1993-01-02
Abstract
Abstract A TV pulse generator for generating television synchronizing and blanking signals and a chrominance subcarrier gating signal. The switchable generator is formed with a clock pulse generator having a frequency which, for the CCIR and the RTMA standards, is 80 times the line frequency. In addition to auxiliary pulses of field frequency, circuits of frequency dividers formed with JK flip-flops and pulse generators also generate auxiliary pulses of line frequency and of double the line frequency. The edges in the synchronizing and blanking signals and in the PAL or NTSC chrominance subcarrier gating signal generated by signal generators are accurately determined by trigger signals derived from the clock pulses.
Inventors
- 👤 Eugenius Martinus Kaptein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:47
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H03; H03K; H03K3/00; H03K3/78; H04N9/00; H04N9/44; H04N9/45
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
140 words
A circuit for generating a television pulse series having pulses of different durations and repetition periods, said circuit comprising a clock pulse source means for supplying pulses having a frequency equal to or an integer multiple of eighty times a selected line frequency, said clock pulse period being substantially to or an integral multiple of the highest common factor of said different pulse periods, the shortest repetition period of said pulses of said series being an integral multiple of said clock pulse period, a plurality of frequency dividers coupled to said clock, a plurality of pulse generators each coupled to at least one of said dividers for control of said generators, a first signal generator having a plurality of inputs coupled to said pulse generators and dividers and an output means for supplying at least part of said pulse series.
Claim 2
Dependent Claim
140 words
A circuit for generating a television pulse series having pulses of different durations and repetition periods, said circuit comprising a clock pulse source means for supplying pulses having a frequency equal to or an integer multiple of eighty times a selected line frequency, said clock pulse period being substantially to or an integral multiple of the highest common factor of said different pulse periods, the shortest repetition period of said pulses of said series being an integral multiple of said clock pulse period, a plurality of frequency dividers coupled to said clock, a plurality of pulse generators each coupled to at least one of said dividers for control of said generators, a first signal generator having a plurality of inputs coupled to said pulse generators and dividers and an output means for supplying at least part of said pulse series.
Claim 3
Dependent Claim
59 words
A circuit as claimed in claim 1 further comprising a second signal generator means for generating a different series from said first generator and synchronized therewith, said clock pulse source having a period equal to or an integer multiple of the highest common factor of the time difference between the pulse series of said first and second signal generators.
Claim 4
Dependent Claim
43 words
A circuit as claimed in claim 1 wherein some of said frequency dividers provide line frequency signals, said signal generator comprising means for generating synchronizing and blanking pulses directly coupled to said line frequency divider for control of the edges of said pulses.
Claim 5
Dependent Claim
53 words
A circuit as claimed in claim 1 wherein said dividers comprise line and field frequency dividers; and further comprising means for providing a long field frequency pulse; a gate having inputs coupled to said long pulse generator and said field frequency dividers, and an output means for supplying a short field frequency pulse.
Claim 6
Dependent Claim
24 words
A circuit as claimed in claim 1 wherein said dividers, pulse generators, and first signal generator each comprise at least one J-K flip-flop circuit.
Claim 7
Dependent Claim
49 words
A circuit as claimed in claim 5 wherein said flip-flops having a propagation delay time and are sequentially arranged, at least one of said flip-flops having two inputs coupled to said clock source and to the outputs of other flip-flops respectively, said other flip-flops having a different sequential number.
Claim 8
Dependent Claim
72 words
A circuit as claimed in claim 5 wherein at least one flip-flop in each of the dividers and pulse generators has a propagation time delay and two trigger action inputs, one of said inputs being coupled to said clock pulse source and one of the sequentially subsequent flip-flops in the divider and pulse generator respectively, the remaining input being coupled to the output of a flip-flop that succeeds the clock pulse source.
Claim 9
Dependent Claim
29 words
A circuit as claimed in claim 5 wherein the J-K flip-flop in said signal generator has J,K, command and reset inputs, all of said inputs having a trigger action.
Claim 10
Dependent Claim
58 words
A circuit as claimed in claim 5 further comprising an auxiliary pulse generator means for providing auxiliary pulses at the line frequency and double said line frequency, said auxiliary generator comprising a J-K flip-flop having a pair of inverse signal outputs with different propagation time delays coupled to the set and reset inputs of said signal generator flip-flop.
Claim 11
Dependent Claim
87 words
A circuit as claimed in claim 5 wherein said dividers comprise line and field frequency dividers; and further comprising means for providing an NTSC chrominance subcarrier gating signal comprising a J-K flip-flop having a command input coupled to said clock pulse source, a first and second preparatory inputs, said first input being coupled to said line frequency dividers, and a reset input; a differentiating circuit coupled between said second input and said signal generator; and means for generating auxiliary field frequency pulses coupled to said reset input.
Claim 12
Dependent Claim
62 words
A circuit as claimed in claim 1 wherein said frequency dividers comprise line and field frequency dividers, first switching means coupled to said field frequency dividers for switching the dividend, and a second switching means coupled to said field frequency dividers for displacing the field pulse edges, the divisor remaining a constant whereby said circuit can be used with different television standards.
Claim 13
Dependent Claim
38 words
A circuit as claimed in claim 11 wherein said line frequency dividers have a greater than necessary divisor and comprise switchable feedback means coupled thereto for reducing said divisor to the proper value and for pulse edge displacement.
Claim 14
Dependent Claim
41 words
A circuit as claimed in claim 11 further comprising means for increasing the divisor of one of said field frequency dividers comprising means for coupling the output of one of said signal generators to a blocking input of said one divider.
Claim 15
Dependent Claim
103 words
A circuit as claimed in claim 1 wherein said dividers comprise line and field frequency dividers and further comprising a PAL chrominance subcarrier gating generator coupled to said line frequency dividers and said clock pulse source, said gating generator comprising a blocking generator means coupled to said field frequency dividers and to one of said signal generators and providing a blocking pulse having a period equal to nine line periods and occurring at the field frequency, said blocking generator having an auxiliary pulse generator means for supplying pulses of one half of the line frequency for pulse edge determination of said blocking generator.
Claim 16
Dependent Claim
73 words
A circuit as claimed in claim 14 wherein said gating generator comprises first and second J-K flip-flops each having a command and reset inputs, and an output, said command inputs being coupled to said clock source and said line frequency dividers respectively, said first output being coupled to said second reset input, said first reset input being coupled to said blocking signal generator, and said second output means for providing said gating signal.
Claim 17
Dependent Claim
79 words
A circuit as claimed in claim 14 wherein said gating signal generator comprises a first J-K flip-flop having a preparatory input coupled to said blocking generator, a command input coupled to said auxiliary pulse generator, a reset input coupled to said line frequency dividers, and an output; and a second J-K flip-flop having a reset input coupled to said first flip-flop output, a command input coupled to said clock source, and an output means for providing said gating signal.
Claim 18
Dependent Claim
43 words
A circuit as claimed in claim 14 wherein said auxiliary generator comprises a J-K flip-flop having a pair of outputs, and said blocking generator comprises a J-K flip-flop having a pair of trigger action preparatory inputs coupled to said auxiliary flip-flop outputs respectively.
Claim 19
Dependent Claim
81 words
A circuit as claimed in claim 1 wherein said dividers comprise line and field frequency dividers, said field frequency dividers comprise an input means adapted to receive a field frequency signal for synchronization of said field frequency dividers, said circuit further comprising a phase discriminator having two inputs for receiving the line frequency signal from said line dividers and a line frequency synchronizing signal, and an output means coupled to said clock pulse source for synchronization of said clock pulse source.
Claim 20
Dependent Claim
37 words
A circuit as claimed in claim 18 further comprising a field synchronizing circuit coupled to said field synchronizing input and wherein one of said pulse generators comprises a field frequency generator coupled to said field synchronizing circuit.
Claim 21
Dependent Claim
83 words
A circuit as claimed in claim 1 wherein at least two of said frequency dividers supply line and field frequency signals respectively, and wherein one of said pulse generators comprise an auxiliary pulse generator means coupled to said line and field dividers for control of said auxiliary generator and for generating pulses of the line frequency and double the line frequency, said auxiliary generator also being coupled to control said signal generator, said signal generator comprising means for generating synchronizing and blanking signals.
Claim 22
Dependent Claim
59 words
A circuit as claimed in claim 20 wherein said auxiliary generator is directly connected to the line frequency divider and wherein at least one of said generators comprises means for generating a pulse lasting one equalizing and one field synchronizing period coupled between said auxiliary generator and said field frequency divider for controlling the frequency of said auxiliary generator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-01-26 | 1979-07-28 | 1980-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-01-26 | 1983-07-28 | 1984-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-01-26 | 1987-07-28 | 1988-01-27 | $7700.00 | Window Closed / Lapsed |