Patent US3935381A successfully refreshed from Google Patents.
US3935381A
Expired / Lapsed
US
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Electronic solid state sensor image size control
Assignee: United States Department of the Navy
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Filing: 1974-06-24
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Granted: 1976-01-27
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Expires: 1994-06-24
Abstract
Abstract An electronic control system for changing the image size produced by solidtate sensors such as the Reticon sensor array, charged coupled devices, etc. The image size is increased or decreased by varying the horizontal and vertical scanning rate with respect to standard TV timing. The scanning rate is controlled by controlling the frequency of the horizontal and vertical clock pulses applied to the solid state sensor.
Inventors
- 👤 Edward A. Petrocelli
- 👤 Anthony C. H. Louie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:38
CPC Classifications
H; H04; H04N; H04N3/00; H04N3/10; H04N3/16; H04N3/22; H04N3/223; H04N25/00; H04N25/40; H04N25/44; H04N25/443; H04N25/70; H04N25/71; H04N25/745
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
181 words
An electronic control system for generating scanning clock signals to control the scanning rate of a solid state sensor to read out the video information and control the image size reproduced on a TV monitor comprising: a. s source of clock frequencies, b. timing circuit means for providing a field synchronizing pulse output and a line synchronizing pulse output; c. first counter circuit means coupled to said source of clock frequencies to provide a scanning clock signal of a predetermined frequency determined by a desired picture size, d. delay circuit means coupled to said timing circuit means for delaying the field and line synchronizing pulses a predetermined time delay, e. variable gate generator circuit means coupled to said delay circuit means and to said first counter means for gating a predetermined number of clock pulses to said solid state sensor corresponding to the size of the sensor array, f. feedback circuit means coupled from said sensor to said variable gate generator circuit means for providing a feedback signal to turn off said variable gate at the end of said predetermined time.
Claim 2
Dependent Claim
181 words
An electronic control system for generating scanning clock signals to control the scanning rate of a solid state sensor to read out the video information and control the image size reproduced on a TV monitor comprising: a. s source of clock frequencies, b. timing circuit means for providing a field synchronizing pulse output and a line synchronizing pulse output; c. first counter circuit means coupled to said source of clock frequencies to provide a scanning clock signal of a predetermined frequency determined by a desired picture size, d. delay circuit means coupled to said timing circuit means for delaying the field and line synchronizing pulses a predetermined time delay, e. variable gate generator circuit means coupled to said delay circuit means and to said first counter means for gating a predetermined number of clock pulses to said solid state sensor corresponding to the size of the sensor array, f. feedback circuit means coupled from said sensor to said variable gate generator circuit means for providing a feedback signal to turn off said variable gate at the end of said predetermined time.
Claim 3
Dependent Claim
71 words
The control system of claim 1 wherein said delay circuit means includes a first delay circuit coupled to the field sync output of said timing circuit means and a second delay circuit coupled through a divide by x counter to the line sync output of said timing circuit means for providing delayed line and vertical sync pulses to establish the position of the start of the horizontal and vertical scan respectively.
Claim 4
Dependent Claim
142 words
The control system of claim 2 wherein said variable gate generator circuit means includes: a. a first flip-flop circuit coupled to the output of said first delay circuit for providing a vertical gate signal, b. a first AND gate having a first input coupled to the output of said first flip-flop circuit and a second input coupled to the output of said second delay circuit for providing an output gate signal, c. a second flip-flop circuit having a first input coupled to the output of said first AND gate for providing an output gate signal, d. a second AND gate having a first input coupled to the output of said second flip-flop circuit and a second input coupled to the source of clock pulses for gating said clock pulses as long as a gate signal is generated by said second flip-flop circuit.
Claim 5
Dependent Claim
45 words
The control system of claim 3 wherein feedback circuit means are coupled from said sensor to said first and second flip-flop circuit means for providing a feedback signal to turn off said flip-flops at the end of the scan of the frame of said sensor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-01-26 | 1979-07-28 | 1980-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-01-26 | 1983-07-28 | 1984-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-01-26 | 1987-07-28 | 1988-01-27 | $7700.00 | Window Closed / Lapsed |