Power surge protection system

Claim 2

A surge suppressor for dissipating power surges impressed upon an electrical line, said suppressor comprising: a. means for dissipating the bulk of the energy for a power surge on the electrical line, said dissipating means having an electrode connected to the electrical line; b. an avalanche semiconductor element connected in parallel with said dissipating means, said avalanche semiconductor element clipping the remaining energy of the power surge impressed upon the electrical line; c. a delay line comprising a series connected inductor and resistor for preventing said avalanche semiconductor element from clamping said dissipating means, said delay line being disposed intermediate said electrode of said dissipating means and said avalanche semiconductor element; whereby the bulk of the power surge impressed upon the electrical line is dissipated by said dissipating means and the remainder of the power surge is clipped by said avalanche semiconductor element.

Claim 3

The suppressor as set forth in claim 1 wherein said dissipating means includes a further electrode; said avalanche semiconductor element includes a first terminal connected to said delay line and a second terminal; and, means for interconnecting said further electrode and said second terminal.

Claim 4

The suppressor as set forth in claim 2 wherein said interconnecting means is grounded.

Claim 5

The suppressor as set forth in claim 1 wherein said dissipating means comprises a spark gap.

Claim 6

The suppressor as set forth in claim 4 wherein said avalanche semiconductor element comprises a pn silicon junction element.

Claim 7

The suppressor as set forth in claim 5 wherein said dissipating means comprises a slow acting semiconductor device.

Claim 8

The suppressor as set forth in claim 4 wherein said avalanche semiconductor element comprises a TransZorb.

Claim 9

A surge suppressor for dissipating power surges on a pair of electrical lines, said suppressor comprising: a. a spark gap having a first electrode connected to one of the pair of electrical lines, a second electrode connected to another of the pair of electrical lines and a grounded electrode common to said first and second electrodes for dissipating the bulk of a power surge impressed upon the pair of electrical lines; b. a pair of avalanche semiconductor elements for clipping the remaining energy of the power surge impressed upon the pair of electrical lines, each of said pair of avalanche semiconductor elements having a grounded terminal and an ungrounded terminal; c. a first delay line comprising a series connected inductor and resistor interconnecting said first electrode with the ungrounded terminal of one of said avalanche semiconductor elements; and d. a second delay line comprising a series connected inductor and resistor interconnecting said second electrode with the ungrounded terminal of another of said avalanche semiconductor elements; whereby, said first and second delay lines electrically segregate the operation of said spark gap and said pair of avalanche semiconductor elements to prevent said pair of avalanche semiconductors from clamping said spark gap.

Claim 10

A surge suppressor for dissipating power surges on a pair of electrical lines, said suppressor comprising: a. a spark gap having a first electrode connected to one of the pair of electrical lines, a second electrode connected to another of the pair of electrical lines and a grounded electrode common to said first and second electrodes for dissipating the bulk of a power surge impressed upon the pair of electrical lines; b. a pair of avalanche semiconductor elements for clipping the remaining energy of the power surge impressed upon the pair of electrical lines, each of said pair of avalanche semiconductor elements having a grounded terminal and an ungrounded terminal; c. a first delay line comprising a series connected inductor and resistor interconnecting said first electrode with the ungrounded terminal of one of said avalanche semiconductor elements; and d. a second delay line comprising a series connected inductor and resistor interconnecting said second electrode with the ungrounded terminal of another of said avalanche semiconductor elements; whereby, said first and second delay lines electrically segregate the operation of said spark gap and said pair of avalanche semiconductor elements to prevent said pair of avalanche semiconductors from clamping said spark gap.

Claim 11

The suppressor as set forth in claim 8 wherein said avalanche semiconductor elements comprise TransZorbs.

Claim 12

The suppressor as set forth in claim 9 wherein said avalanche semiconductor elements comprise TransZorbs connected back-to-back.