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US3932767A
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Filter-discriminator circuit
Assignee: CLARK SHERRY B (BOTH AS JOINT TENANTS)
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Filing: 1973-07-23
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Granted: 1976-01-13
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Expires: 1993-07-23
Abstract
Abstract A train of pulses introduced into a filter-discriminator circuit is processed therein, the amplitudes of adjacent pulses in the input train being compared against one another deriving an output signal from that comparison whose amplitudes equal the differences in amplitude between adjacent pulses. Adjacent pulses in the train of like amplitude, produce only low amplitude transient signals that are mostly blanked out by circuitry within the discriminator. By connecting a second filter-discriminator circuit in series with the first, the output therefrom will produce a signal having peak or spike pulses therein whose amplitudes equal the double derivative of unlike pulses in the train of pulses. The output peak of spike pulses can then be used as trigger pulses keying timer and associated circuitry.
Inventors
- 👤 Thiel J. Gomm
- 👤 Stephen E. Price
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:59
CPC Classifications
H; H03; H03K; H03K9/00; H03K9/02; G; G01; G01N; G01N21/00; G01N21/84; G01N21/88; G01N21/89
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
159 words
A filter-discriminator circuit comprising: means for providing a train of pulses, the amplitude of each of which pulses is to be compared against adjacent pulses in the train; a first sample and hold circuit that receives the train of pulses and extends the period of the pulses in said train; a second sample and hold circuit adapted to receive the signal output from said first sample and hold circuit and having means for delaying the signal passage therethrough by approximately the period of one input pulse; a difference amplifier that receives the signal outputs from both the first and second sample and hold circuits comparing these signal outputs with one another producing, from that comparison, an output signal having pulses whose amplitudes equal the differences in amplitudes between compared pulses; and clock means connected to said means for providing a train of pulses and to the difference amplifier for synchronizing the signal outputs with the input train of pulses.
Claim 2
Dependent Claim
159 words
A filter-discriminator circuit comprising: means for providing a train of pulses, the amplitude of each of which pulses is to be compared against adjacent pulses in the train; a first sample and hold circuit that receives the train of pulses and extends the period of the pulses in said train; a second sample and hold circuit adapted to receive the signal output from said first sample and hold circuit and having means for delaying the signal passage therethrough by approximately the period of one input pulse; a difference amplifier that receives the signal outputs from both the first and second sample and hold circuits comparing these signal outputs with one another producing, from that comparison, an output signal having pulses whose amplitudes equal the differences in amplitudes between compared pulses; and clock means connected to said means for providing a train of pulses and to the difference amplifier for synchronizing the signal outputs with the input train of pulses.
Claim 3
Dependent Claim
28 words
A filter-discriminator circuit as recited in claim 1, further including means for providing a signal for blanking out transient signals from the signal output of the difference amplifier.
Claim 4
Dependent Claim
55 words
A first filter-discriminator circuit as recited in claim 1, including a second filter-discriminator circuit connected in series with a said first filter-discriminator circuit, the signal output from said first filter-discriminator circuit being further compared within said second filter discriminator circuit, producing a signal output equal to the double derivative of the input train of pulses.
Claim 5
Dependent Claim
60 words
A filter-discriminator circuit as recited in claim 1, wherein the first and second sample and hold circuits each contain capacitors that are charged by each incoming pulse, which charge is held, and then dumped by the introduction of a dumping pulse; and means connected to the clock means and in series with each said capacitor for providing timed dumping pulses.
References Cited (Backward Citations)
US3116458A
Cited
US3508158A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-01-12 | 1979-07-14 | 1980-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-01-12 | 1983-07-14 | 1984-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-01-12 | 1987-07-14 | 1988-01-13 | $7700.00 | Window Closed / Lapsed |