Sampling automatic equalizer

Claim 2

An automatic tranversal equalizer including means for sampling an input signal, a plurality of capacitors for storing the sampled input signal in sequence, a further plurality of capacitors for storing tap coefficient voltages derived from the output of the equalizer, means for sequentially updating said further plurality of capacitors, and a single multiplier having a first input connected to receive said data samples stored by the first mentioned plurality of capacitors in a predetermined sequence, and a second input for receiving the coefficient tap voltages stored by said further plurality of capacitors in a predetermined sequence and for providing an output in accordance with the product of said data samples and said coefficient tap voltages.

Claim 3

A equalizer as claimed in claim 1 further comprising an integrator means for summing the outputs of said multiplier means and means for resetting said integrator to zero at a rate which is a multiple of the data baud rate.

Claim 4

An equalizer as claimed in claim 2 further comprising a sample and hold circuit for sampling and holding the output of said integrator means to produce an equalizer output signal.

Claim 5

An equalizer as claimed in claim 3 further comprising means for selecting said further plurality of capacitors in sequence comprising divide by N counter means which counts from 0 to N-1, where N is the number of taps of the equalizer.

Claim 6

An equalizer as claimed in claim 4 which provides one data sample per baud operation, said equalizer further comprising means for selecting the first mentioned plurality of capacitors in sequence comprising counter means for counting from 0 to N-1.

Claim 7

An equalizer as claimed in claim 4 which provides two sample per baud operation, said equalizer further comprising means for selecting the first mentioned capacitors in sequence comprising counter means for counting from 0 to 2N-1.

Claim 8

An equalizer as claimed in claim 4 which provides four data samples per baud, said equalizer further comprising means for selecting the first mentioned capacitors in sequence comprising counter means for counting from 0 to 4N-1.

Claim 9

An automatic transversal equalizer comprising means for sampling the input signal to the equalizer, a first plurality of capacitors for storing the sampled voltages in a predetermined sequence, a further plurality of capacitors for storing internally generated coefficient voltages derived from the output of the equalizer, a single multiplier having first and second inputs for producing an output in accordance with the product of the voltage inputs thereto, switching means for applying said sampled voltages and said coefficient voltages to respective ones of said first and second inputs of said multiplier in predetermined sequence, and integrator means for integrating the output of said multiplier.

Claim 10

An automatic transversal equalizer comprising means for sampling the input signal to the equalizer, a first plurality of capacitors for storing the sampled voltages in a predetermined sequence, a further plurality of capacitors for storing internally generated coefficient voltages derived from the output of the equalizer, a single multiplier having first and second inputs for producing an output in accordance with the product of the voltage inputs thereto, switching means for applying said sampled voltages and said coefficient voltages to respective ones of said first and second inputs of said multiplier in predetermined sequence, and integrator means for integrating the output of said multiplier.

Claim 11

An automatic transversal equalizer as claimed in claim 8 further comprising a sample and hold circuit for sampling and holding the output of said integrator means.

Claim 12

An automatic transversal equalizer as claimed in claim 9 wherein said switching means comprises MOS analog switch means.

Claim 13

An automatic transversal equalizer as claimed in claim 10 wherein said MOS analog switch means comprises means comprising first counter means, responsive to the baud clock of the equalizer and a first MOS analog switch, for controlling the switching sequence of said coefficient voltages and means, comprising logic circuit means responsive to said first counter means, second counter means responsive to said logic circuit means and said baud clock and a second MOS analog switch, for controlling the switching sequence of said sampled voltages.

Claim 14

An automatic transversal equalizer comprising means for sampling an input signal, a plurality of discrete capacitors connected in parallel to form a bank of capacitors for storing the samples of said input signal, switching means for cyclically and sequentially retrieving the samples stored by said capacitors in a predetermined sequence, the samples stored by said capacitors being retrieved during at least two successive cycles, means for deriving a series of coefficient voltages from the output of the equalizer, and multiplier means for sequentially multiplying the samples retrieved by said switching means with said series of coefficient voltages to produce an output in accordance with the product of said retrieved samples and said coefficient voltages.

Claim 15

An automatic transversal equalizer comprising means for sampling an input signal, a plurality of discrete capacitors connected in parallel to form a bank of capacitors for storing the samples of said input signal, switching means for cyclically and sequentially retrieving the samples stored by said capacitors in a predetermined sequence, the samples stored by said capacitors being retrieved during at least two successive cycles, means for deriving a series of coefficient voltages from the output of the equalizer, and multiplier means for sequentially multiplying the samples retrieved by said switching means with said series of coefficient voltages to produce an output in accordance with the product of said retrieved samples and said coefficient voltages.