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US3931545A Expired / Lapsed US ⏱️ 0.0 years remaining

Horizontal deflection circuit

Assignee: REDACTRON CORP
•
Filing: 1974-12-13
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Granted: 1976-01-06
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Expires: 1994-12-13
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Abstract

Abstract The current flowing through the horizontal deflection coil of a cathod ray tube is controlled by a transistor which is switched between saturation and cut off by a circuit having a pulse generator for generating a pulse in response to a horizontal synchronizing pulse. The leading edge of the generated pulse is delayed before being applied to the controlling transistor which switches sometime thereafter due to the storage time of the transistor. To insure that the blanking of the electron beam of the tube takes place during the retrace time, the blanking interval is set to occur a period of time after the horizontal synchronizing signal which is less than the sum of the storage time of the transistor and the time which the leading edge of the generated pulse is delayed.

Inventors

  • 👤 Francis C. Marino

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 21:51
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/06; H03K4/08; H03K4/48; H03K4/60; H03K4/62; H03K4/64; H04; H04N; H04N3/00; H04N3/10; H04N3/16

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 246 words
In a cathode ray tube display device having a horizontal deflection coil through which current flows under control of a first transistor which is switched between a saturation state and a cut off state to establish the sweep and retrace portions of a line scan, apparatus for controlling the switching of the first transistor between the states and for generating a blanking signal which occurs during the retrace portions of the line scans comprising means for generating a horizontal synchronizing signal, means for generating a blanking signal of a given time duration and at a first predetermined period of time after the generation of a horizontal synchronizing signal, said first predetermined period of time being greater than the maximum storage time of the first transistor, a pulse generator means having an input terminal and an output terminal for generating a pulse at said output terminal each time a signal is received at said input terminal, a passive delay means connected to said output terminal for delaying at least the leading edge of a pulse generated by said pulse generator means for a second predetermined period of time, and applying means for applying the pulse delayed by said passive delay means to said first transistor to control the switching thereof, said second predetermined period of time being chosen so that the sum of the storage time of said first transistor plus the said second predetermined period of time is greater than said first predetermined period of time.
Claim 2
Dependent Claim 246 words
In a cathode ray tube display device having a horizontal deflection coil through which current flows under control of a first transistor which is switched between a saturation state and a cut off state to establish the sweep and retrace portions of a line scan, apparatus for controlling the switching of the first transistor between the states and for generating a blanking signal which occurs during the retrace portions of the line scans comprising means for generating a horizontal synchronizing signal, means for generating a blanking signal of a given time duration and at a first predetermined period of time after the generation of a horizontal synchronizing signal, said first predetermined period of time being greater than the maximum storage time of the first transistor, a pulse generator means having an input terminal and an output terminal for generating a pulse at said output terminal each time a signal is received at said input terminal, a passive delay means connected to said output terminal for delaying at least the leading edge of a pulse generated by said pulse generator means for a second predetermined period of time, and applying means for applying the pulse delayed by said passive delay means to said first transistor to control the switching thereof, said second predetermined period of time being chosen so that the sum of the storage time of said first transistor plus the said second predetermined period of time is greater than said first predetermined period of time.
Claim 3
Dependent Claim 60 words
The apparatus of claim 1 wherein said pulse generator means comprises a retriggerable monostable multivibrator having an input terminal which is the input terminal of said pulse generator means and further comprising means for applying a signal associated with the leading edge of the pulse delayed by said passive delay means to said input terminal of said retriggerable monostable multivibrator.
Claim 4
Dependent Claim 23 words
The apparatus of claim 2 wherein said passive delay means only delays the leading of the pulse generated by said retriggerable monostable multivibrator.
Claim 5
Dependent Claim 18 words
The apparatus of claim 3 wherein said passive delay means includes means for controllably varying the delay time.
Claim 6
Dependent Claim 80 words
The apparatus of claim 2 wherein said passive delay means comprises a further transistor having an emitter, a collector and a base, means for applying operating potentials to said further transistor, a resistor connected between said emitter and said base, a network including a capacitor and a second resistor and a diode connected between said base, and the output of said retriggerable monostable multivibrator, and connecting means for connecting said collector to the input terminal of said retriggerable monostable multivibrator.
Claim 7
Dependent Claim 14 words
The apparatus of claim 5 wherein said connecting means comprises a signal differentiating means.
Claim 8
Dependent Claim 36 words
The apparatus of claim 5 wherein said applying means comprises a transformer having a primary winding connected to the collector of said further transistor and a secondary winding connected to the base of said first transistor.
Claim 9
Dependent Claim 45 words
The apparatus of claim 7 wherein said connecting means comprises a capacitor connecting the collector of said further transistor to the input terminal of said retriggerable monostable multivibrator and a resistor connecting the junction of said capacitor and said input terminal to a voltage source.

References Cited (Backward Citations)

US3414668A Cited
US3551733A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-01-05 1979-07-07 1980-01-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-01-05 1983-07-07 1984-01-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-01-05 1987-07-07 1988-01-06 $7700.00 Window Closed / Lapsed

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