Patent US3930203A successfully refreshed from Google Patents.
US3930203A
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Circuit arrangement for adjusting the phase state of a timing signal
Assignee: Siemens AG
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Filing: 1974-10-29
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Granted: 1975-12-30
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Expires: 1994-10-29
Abstract
Abstract Apparatus for adjusting the phase state of a timing signal used, for example, to synchronize a data receiver in a data transmission system is described. The timing signal is obtained from a divider signal. A discriminator signal from the phase state of a binary signal and pulse edges are added to or suppressed from the divider signal. A switching stage is caused to assume one of two states in dependence on the value of the discriminator signal. Parts of the divider signal are conducted over a first channel and a phase reversing stage or a second channel to the input of the frequency divider, from the output of which the timing signal is emitted.
Inventors
- 👤 Adolf Haass
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:49
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
119 words
Apparatus for adjusting the phase state of a timing signal which has been obtained by means of a frequency divider from a divider signal, wherein a discriminator signal is produced in dependence on the phase state of a binary signal and wherein pulse edges of the divider signal are added to or suppressed from the divider signal, comprising: polarity reversal means, first channel means connecting said divider signal to said polarity reversal means and then to an input of said frequency divider, second channel means connecting said divider signal to an input of said frequency divider, switching means for selectively connecting said divider signal to said first or second channel in dependence on the value of said discriminator signal.
Claim 2
Dependent Claim
119 words
Apparatus for adjusting the phase state of a timing signal which has been obtained by means of a frequency divider from a divider signal, wherein a discriminator signal is produced in dependence on the phase state of a binary signal and wherein pulse edges of the divider signal are added to or suppressed from the divider signal, comprising: polarity reversal means, first channel means connecting said divider signal to said polarity reversal means and then to an input of said frequency divider, second channel means connecting said divider signal to an input of said frequency divider, switching means for selectively connecting said divider signal to said first or second channel in dependence on the value of said discriminator signal.
Claim 3
Dependent Claim
35 words
The apparatus defined in claim 1 wherein said switching means is constructed to respond to said discriminator signal to switch between two edges of said divider signal when said binary signal leads said timing signal.
Claim 4
Dependent Claim
32 words
The apparatus defined in claim 1 wherein said switching means is constructed to respond to said discriminator signal to switch simultaneously with the appearance of two pulse edges of said divider signal.
Claim 5
Dependent Claim
60 words
The apparatus defined in claim 1, further comprising: discriminator means for producing said discriminator signal in dependence on the pulse edges of said binary signal in such manner that in the event of leading and lagging edges of said binary signal, and edge of said discriminator signal does and does not, respectively, coincide with an edge of said divider signal.
Claim 6
Dependent Claim
36 words
The apparatus defined in claim 1 wherein said polarity reversal means is an EXCLUSIVE-OR gate having inputs connected to receive said divider signal and said discriminator signal and having an output connected to said frequency divider.
Claim 7
Dependent Claim
70 words
The apparatus defined in claim 1 further comprising: an additional frequency divider emitting an additional divider signal, and additional EXCLUSIVE-OR gate having inputs connected to receive said additional divider signal and said timing signal, a trigger stage having a first input connected to receive the output of said EXCLUSIVE-OR gate and a second input connected to receive said binary signal, the output of said trigger stage emitting said discriminator signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-29 | 1979-06-30 | 1979-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-29 | 1983-06-30 | 1983-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-29 | 1987-06-30 | 1987-12-30 | $7700.00 | Window Closed / Lapsed |