Code translation arrangement

Claim 2

A pulse density modulation to pulse code modulation translation arrangement comprising: a source of pulse density modulated signal; a digital filter coupled to said source; and logic circuitry coupled to said digital filter, said logic circuitry selecting every mth group of n pulses in the output of said digital filter, where m and n are each integers greater than one; said digital filter including a first non-recursive multi-section filter stage having a plurality of unity gain taps, said first filter stage being coupled to said source, a first summing gate coupled in common to all of said taps of said first filter stage, a second non-recursive multi-section filter stage having a plurality of unity gain taps, said second filter stage being coupled to the output of said first gate, and a second summing gate coupled in common to all of said taps of said second filter stage, the output of said second gate being coupled to said logic circuitry.

Claim 3

A pulse density modulation to pulse code modulation translation arrangement comprising: a source of pulse density modulated signal; a digital filter coupled to said source; and logic circuitry coupled to said digital filter, said logic circuitry selecting every mth group of n pulses in the output of said digital filter, where m and n are each integers greater than one; said digital filter including a first non-recursive multi-section filter stage having a plurality of taps with increasingly weighted gain from unity gain at a first of said taps, said first filter stage being coupled to said source, a first summing gate coupled in common to each of said taps of said first filter stage, a delay means coupled to the output of said first gate, a subtracting means coupled to the output of said delay means and the output of said first gate, a second non-recursive multi-section filter stage having a plurality of unity gain taps, said second filter stage being coupled to said source, a second summing gate coupled in common to each of said taps of said second filter stage, and a third summing gate coupled to the output of said second gate and said subtracting means to provide an output signal coupled to said logic circuitry.

Claim 4

A pulse density modulation to pulse code modulation translation arrangement comprising: a source of pulse density modulated signal; a digital filter coupled to said source; and logic circuitry coupled to said digital filter, said logic circuitry selecting every mth group of n pulses in the output of said digital filter, where m and n are each integers greater than one; said digital filter including a first non-recursive multi-section filter stage having a plurality of taps with increasingly weighted gain from unity gain at a first of said taps, said first filter stage being coupled to said source, a first summing gate coupled in common to each of said taps of said first filter stage, a delay means coupled to the output of said first gate, a subtracting means coupled to the output of said delay means and the output of said first gate, a second non-recursive multi-section filter stage having a plurality of unity gain taps, said second filter stage being coupled to said source, a second summing gate coupled in common to each of said taps of said second filter stage, and a third summing gate coupled to the output of said second gate and said subtracting means to provide an output signal coupled to said logic circuitry.

Claim 5

An arrangement according to claim 2, wherein said first filter stage includes a clocked digital up-counter coupled to said source, a register, and an accumulator coupled between said clocked up-counter and said register to keep adding the contents of said clocked up-counter to said register in accordance with said pulse density modulated signal.

Claim 6

An arrangement according to claim 3, wherein said second filter stage includes an up-counter coupled to said source, said up-counter being incremented by said pulse densiTy modulated signal, first means coupled to said up-counter to periodically clear said up-counter, and second means coupled to said up-counter to multiply the contents of said up-counter immediately prior to each clearing of said up-counter.

Claim 7

An arrangement according to claim 2, wherein said second filter stage includes an up-counter coupled to said source, said up-counter being incremented by said pulse density modulated signal, first means coupled to said up-counter to periodically clear said up-counter, and second means coupled to said up-counter to multiply the contents of said up-counter immediately prior to each clearing of said up-counter.