Patent US3928798A successfully refreshed from Google Patents.
US3928798A
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Means for frequency/digital conversion
Assignee: ABB Norden Holding AB
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Filing: 1974-10-07
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Granted: 1975-12-23
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Expires: 1994-10-07
Abstract
Abstract An arrangement for frequency/digital conversion, particularly for digital revolution and speed measuring, includes a clock unit, a control unit, and a counter unit. The clock unit provides a pulse train with a constant frequency. A multiplying unit is provided which gives a second pulse train, the frequency of which is dependent on the product of the constant frequency and the latest maximum value of the contents of the counter unit. The contents of the counter unit are reduced by a first quantity upon each pulse of the second pulse train. Another unit is arranged to supply the control unit with a third pulse train with an unknown frequency. The control unit emits a control signal to the counter unit for each pulse in the third pulse train. The counter unit increases its contents by a second quantity at the occurrence of such control signal. The second quantity is greater than or equal to the first quantity. After each such addition, the contents of the counter unit reach a new maximum value which constitutes a digital representation of the frequency of the second pulse train.
Inventors
- 👤 Jaroslav Valis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:30
CPC Classifications
G; G01; G01P; G01P3/00; G01P3/42; G01P3/44; G01P3/48; G01P3/481; G01P3/489; G01R; G01R23/00; G01R23/02; G01R23/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
238 words
Apparatus from frequency/digital conversion, especially for digital revolution and speed measuring, which comprises a clock unit (CLC), a control unit (SCL), and a counter unit (UDC), the clock unit (CLC) including means to deliver a first pulse train (CP) with a constant frequency (fC), in which the apparatus comprises a multiplying unit (DRM) including means to deliver to the control unit a second pulse train (FR), the frequency of which (fR) is dependent on the product of said constant frequency (fC) and the latest maximum value (F) of the contents (G) of the counter unit (UDC), the counter unit (UDC) including means to reduce its contents (G) by a first quantity (N1) in response to each pulse in the second pulse train (FR), another unit (PU) including means to supply the control unit (SCL) with a third pulse train (FX) with an unknown frequency (fX), the control unit (SCL) including means to emit a control signal to the counter unit (UDC) for each pulse in the third pulse train, the counter unit (UDC) increasing its contents (G) by a second quantity (N2) at the occurrence of said control signal, said second quantity (N2) being greater than or equal to said first quantity (N1), and after each such addition the contents (G) of the counter unit (UDC) having reached a new maximum value (F) which constitutes a digital representation of the frequency (fX) of the second pulse train (FX).
Claim 2
Dependent Claim
238 words
Apparatus from frequency/digital conversion, especially for digital revolution and speed measuring, which comprises a clock unit (CLC), a control unit (SCL), and a counter unit (UDC), the clock unit (CLC) including means to deliver a first pulse train (CP) with a constant frequency (fC), in which the apparatus comprises a multiplying unit (DRM) including means to deliver to the control unit a second pulse train (FR), the frequency of which (fR) is dependent on the product of said constant frequency (fC) and the latest maximum value (F) of the contents (G) of the counter unit (UDC), the counter unit (UDC) including means to reduce its contents (G) by a first quantity (N1) in response to each pulse in the second pulse train (FR), another unit (PU) including means to supply the control unit (SCL) with a third pulse train (FX) with an unknown frequency (fX), the control unit (SCL) including means to emit a control signal to the counter unit (UDC) for each pulse in the third pulse train, the counter unit (UDC) increasing its contents (G) by a second quantity (N2) at the occurrence of said control signal, said second quantity (N2) being greater than or equal to said first quantity (N1), and after each such addition the contents (G) of the counter unit (UDC) having reached a new maximum value (F) which constitutes a digital representation of the frequency (fX) of the second pulse train (FX).
Claim 3
Dependent Claim
45 words
Apparatus according to claim 1, in which the frequency (fR) of the second pulse train (FR) is equal to the product of said constant frequency (fC) and said maximum value (F) divided by a proportionality constant (M) which is greater than said maximum value (F).
Claim 4
Dependent Claim
55 words
Apparatus according to claim 1, which comprises a register unit (RL) connected between and to the counter unit (UDC) and the multiplying unit (DRM), said register unit including means to memorize a first maximum value (Fk) of the contents (G) in the counter unit (UDC) until a second maximum value (Fk 1) has been obtained.
Claim 5
Dependent Claim
25 words
Apparatus according to claim 1, in which the ratio between said first quantity (N1) and said second quantity (N2) is 10p, p being an integer.
Claim 6
Dependent Claim
25 words
Apparatus according to claim 1, in which the ratio between said first quantity (N1) and said second quantity (N2) is 16q, q being an integer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-22 | 1979-06-23 | 1979-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-22 | 1983-06-23 | 1983-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-22 | 1987-06-23 | 1987-12-23 | $7700.00 | Window Closed / Lapsed |