Logical circuit with field effect transistors

Claim 2

A binary frequency divider stage circuit with insulated gate field effect transistors (MOST) powered by a constant voltage source, comprising an input I for introducing an input signal and at least three logical nodes, each logical node being an interconnection between the drains of at least one n-channel MOST and at least one p-channel MOST, each logical node being connected to control means of at least one other node and being able to be used as an output, the source of one of the MOST (1) of at least one of the nodes (A) being connected to one terminal of the voltage source and the source of the other MOST (A) of the same node being connected to the drain of a third MOST (2), the source of which is connected to the other terminal of the voltage source, the node (A) establishing the interconnection between the drains of the p- and n-channel MOST being controlled by two variables, one being the input signal and the other being the signal from an other logical node (E), in such a way that one variable (I) drives the gates of the third MOST (2) and one pchannel MOST, and the other variable drives the gate of the nchannel MOST (4), allowing the corresponding node to float when this transistor (4) as well as the complementary transistor (1) driven by the other variable are both blocked.

Claim 3

A circuit according to claim 1, comprising a positive terminal (PT), a negative terminal (NT), an input (I), an output (E), nine field effect transistors five of which (2, 4, 8, 10, 12) are n-channel and the other four of which (1, 5, 9, 13) are p-channel, each of said transistors comprising a sources (S1, etc.), a gate (G1, etc.), and a drain (D1, etc), the circuit being connected as follows: the positive terminal (PT) is connected to the source (S1) of transistor 1, to the source (S5) of transistor 5 and to the source (S13) of transistor 13; the negative terminal (NT) is connected to the source (S2) of transistor 2 and to the source (S10) of transistor 10; the ouTput (E) is connected to the drain (D8) of transistor 8, to the drain (D9) of transistor 9 and to the gate (G4) of transistor 4; the input (I) is connected to the gate (G1) of transistor 1, to the gate (G2) of transistor 2, to the gate (G5) of transistor 5 and to the gate (G12) of transistor 12; the drain (D1) of transistor 1 is connected to the drain (D4) of transistor 4, to the gate (G10) of transistor 10 and to the gate (G13) of transistor 13; the drain (D12) of transistor 12 is connected to the drain (D13) of transistor 13, to the gate (G8) of transistor 8 and to the gate (G9) of transistor 9; the drain (D10) of transistor 10 is connected to the source (S8) of transistor 8 and to the source (S12) of transistor 12; the drain (D5) of transistor 5 is connected to the source (S9) of transistor 9; and the drain (D2) of transistor 2 is connected to the source (S4) of transistor 4.