Current mirror and degenerative amplifier

Claim 2

In combination: a current mirror including an input terminal, an output terminal, a common terminal, and bipolar transistors, said bipolar transistors of said current mirror having distributed capacitance between base and emitter electrodes which tends to deteriorate the high-frequency performance of said transistor; means for counteracting said tendency comprising a field effect transistor having a source electrode connected to the output terminal of said current mirror, a gate electrode coupled to the input terminal of said current mirror, and a drain electrode; a current supply connected between the input terminal of said current mirror and a point of reference potential; and a load connected between said drain electrode and said point of reference potential.

Claim 3

The combination of claim 1, wherein an input terminal receptive of an input signal is coupled to the gate electrode of said field effect transistor to provide a degenerative field effect transistor amplifier.

Claim 4

The combination of claim 1, wherein said current mirror and said field effect transistor are fabricated as an integrated circuit.

Claim 5

The combination of claim 1, wherein a resistor is used to couple the gate electrode of said field effect transistor and a terminal of the current supply to the input terminal of said current mirror, said resistor providing decoupling of the interelectrode capacitance of said bipolar transistors from said field effect transistor and current supply, enhancing the high-frequency performance of said combination.

Claim 6

The combination of claim 1, wherein said field effect transistor is a metal-oxide-semiconductor field effect transistor.

Claim 7

In combination: a first bipolar transistor connected at its emitter to a common terminal, and at its collector to an input terminal; diode means connected at one electrode to said common terminal, and at its other electrode to both an output terminal and a base electrode of said bipolar transistor; a current supply coupled between the input terminal of said bipolar transistor and a point of reference voltage; said bipolar transistor having distributed capacitance between its electrodes, said diode having distributed capacitance between its electrodes, the capacitances of said diode and transistor tending to reduce the high-frequency gain of said combination of said bipolar transistor and diode means; load means connected at one terminal to said point of reference voltage; and a field effect transistor having a source electrode connected to said output terminal, a gate electrode coupled to the input terminal of said first bipolar transistor, and a drain electrode connected to the other terminal of said load means, for counteracting said reduction in high-frequency gain, and for providing greater gain with extended frequency response.

Claim 8

In combination: a first bipolar transistor connected at its emitter to a common terminal, and at its collector to an input terminal; diode means connected at one electrode to said common terminal, and at its other electrode to both an output terminal and a base electrode of said bipolar transistor; a current supply coupled between the input terminal of said bipolar transistor and a point of reference voltage; said bipolar transistor having distributed capacitance between its electrodes, said diode having distributed capacitance between its electrodes, the capacitances of said diode and transistor tending to reduce the high-frequency gain of said combination of said bipolar transistor and diode means; load means connected at one terminal to said point of reference voltage; and a field effect transistor having a source electrode connected to said output terminal, a gate electrode coupled to the input terminal of said first bipolar transistor, and a drain electrode connected to the other terminal of said load means, for counteracting said reduction in high-frequency gain, and for providing greater gain with extended frequency response.

Claim 9

The combination of claim 6, wherein said diode means includes a diode connected second bipolar transistor having an emitter electrode connected to said common terminal, a base electrode and a collector electrode connected in comMon to said output terminal and to the base electrode of said first bipolar transistor.

Claim 10

The combination of claim 6, wherein said first bipolar transistor, diode means, and field effect transistor are fabricated as an integrated circuit.

Claim 11

The combination of claim 6, which further includes a signal input terminal receptive of an input signal, coupled to the gate electrode of said field effect transistor, for providing a degenerative field effect transistor amplifier.

Claim 12

The combination of claim 6, which further includes a resistor connected at its one end to said input terminal, and at its other end to said current supply and the gate electrode of said field effect transistor, said resistor providing decoupling of said distributed capacitance of said bipolar transistor from said current supply and field effect transistor, improving the high-frequency performance of said combination.

Claim 13

The combination of claim 6, wherein said field effect transistor is a metal-oxide-semiconductor field effect transistor.

Claim 14

A degenerative field effect transistor amplifier comprising: a first field effect transistor having gate, source, and drain electrodes, said drain electrode being connected to an output terminal, said gate electrode being coupled to an input terminal receptive of an input signal; and current mirror means coupled between the gate and source electrodes of said field effect transistor for degeneratively lowering the source impedance of said field effect transistor to substantially maintain the magnitude of the output current from said amplifier as the frequency of the input signal increases, and for establishing the quiescent operating point of said field effect transistor.

Claim 15

A degenerative field effect transistor amplifier comprising: a first field effect transistor having gate, source, and drain electrodes, said drain electrode being connected to an output terminal, said gate electrode being coupled to an input terminal receptive of an input signal; and current mirror means coupled between the gate and source electrodes of said field effect transistor for degeneratively lowering the source impedance of said field effect transistor to substantially maintain the magnitude of the output current from said amplifier as the frequency of the input signal increases, and for establishing the quiescent operating point of said field effect transistor.

Claim 16

The degenerative field effect transistor amplifier of claim 12, wherein said current mirror means includes: semiconductor unidirectional current means through which a substantial portion of an output current flows for establishing a first control voltage, said unidirectional current means being coupled between a common terminal and the source electrode of said field effect transistor; bipolar transistor means through which a substantial portion of a control current flows for establishing a second control voltage at the gate electrode of said field effect transistor, said bipolar transistor means having a main current carrying path coupled between said common terminal and the gate electrode of said field effect transistor, and having a control terminal receptive of said first control voltage; and impedance means for establishing the magnitude of said control current, said impedance means being connected between the gate electrode of said field effect transistor and a point of reference voltage.

Claim 17

The degenerative field effect transistor amplifier of claim 13, wherein said semiconductor unidirectional current means includes a bipolar transistor that is diode connected, said bipolar transistor having an emitter electrode connected to said common terminal, a base electrode commonly connected to a collector electrode, to the control terminal of said bipolar transistor means, and to the source electrode of said field effect transistor.

Claim 18

The degenerative field effect transistor amplifier of claim 13, wherein said semiconductor unidirectional current means includes a diode having one electrode into which said output current flows, and another electrode from which said output current flows.

Claim 19

The degenerative field effect transistor amplifier of claim 13, wherein said bipolar transistor means includes a bipolar transistor having an emitter electrode connected to said common terminal, a base electrode connected as said control terminal and to the source electrode of said field effect transistor, and a collector electrode coupled to the gate electrode of said field effect transistor.

Claim 20

The degenerative field effect transistor amplifier of claim 12, wherein said field effect transistor and said current mirrow means are fabricated as an iNtegrated circuit.

Claim 21

The degenerative field effect transistor amplifier of claim 16, wherein a resistor is connected from the gate electrode of said field effect transistor to both said impedance means and the collector electrode of said bipolar transistor, said resistor providing decoupling of interelectrode capacitances of said bipolar transistor from said field effect transistor, to improve the high-frequency response of said amplifier.

Claim 22

The degenerative field effect transistor amplifier of claim 12, which further includes: field effect transistor means cascoded with said first field effect transistor for providing a very high output impedance, and for reducing the effective feedback capacitance.

Claim 23

The degenerative field effect transistor amplifier of claim 19, wherein said field effect transistor means includes: a second field effect transistor having a source electrode connected to the output terminal of said first field effect transistor, a drain electrode connected to a load, and a gate electrode; and resistive voltage divider network means connected between said power input terminal and said point of reference voltage for biasing the gate electrode of said second field effect transistor.

Claim 24

The degenerative amplifier of claim 20, wherein said first and second field effect transistors are each a metal-oxide-semiconductor field effect transistor.

Claim 25

The combination of: an input terminal, an output terminal, and a common terminal; a bipolar transistor having base, emitter, and collector electrodes, connected at its emitter electrode to said common terminal; first resistor means, said first resistor means connecting said collector electrode to said input terminal; a diode connected between said common terminal and the base electrode of said transistor, in the forward direction relative to the emitter-base junction of said transistor; and a first field effect transistor having a conduction path and a control electrode, said conduction path being connected between said base electrode and said output terminal, and said control electrode being coupled to said input terminal.

Claim 26

The combination of: an input terminal, an output terminal, and a common terminal; a bipolar transistor having base, emitter, and collector electrodes, connected at its emitter electrode to said common terminal; first resistor means, said first resistor means connecting said collector electrode to said input terminal; a diode connected between said common terminal and the base electrode of said transistor, in the forward direction relative to the emitter-base junction of said transistor; and a first field effect transistor having a conduction path and a control electrode, said conduction path being connected between said base electrode and said output terminal, and said control electrode being coupled to said input terminal.

Claim 27

The combination of claim 22, further including: seconds resistor means, said second resistor means coupling said control electrode to said input terminal; and a signal input terminal at the connection between said resistor means and said control electrode.

Claim 28

The combination of claim 23, further including: a second field effect transistor having a conduction path and a control electrode, said conduction path being connected in series with and between the conduction path of said first field effect transistor and said output terminal; and a pair of resistors connected in series as a resistive voltage divider between said common terminal and a point of reference potential, the common connection point between said pair of resistors being connected to the control electrode of and for biasing said second field effect transistor.