Patent US3924080A successfully refreshed from Google Patents.
US3924080A
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Zero suppression in pulse transmission systems
Assignee: AT&T Inc
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Filing: 1974-12-02
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Granted: 1975-12-02
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Expires: 1994-12-02
Abstract
Abstract An algorithm and circuit arrangement is shown for suppressing unduly long successions of ZEROs in a pulse transmission system by recording the occurrence of most recently occurring ONEs, using a state encoding mechanism such as a counter. If a sequence of ZEROs occurs which would extend the ZEROs to the group succeeding the group initiated by the most recently occurring ONE, a ONE is forced in the last position of the succeeding group. Thereafter, a ONE must be forced at the end of each succeeding group in which a ONE does not naturally occur. If two ONEs occur naturally in any such succeeding group, the second ONE restarts the entire process as described above. The size of the group is chosen to meet minimum pulse density requirements of the connected pulse transmission system.
Inventors
- 👤 James Lewis Caldwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:17
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904; H04L25/4906; H04L25/4915
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
3 words
counting pulse positions,
Claim 2
Dependent Claim
3 words
counting pulse positions,
Claim 3
Dependent Claim
9 words
counting successive pulse positions in which no pulses occur;
Claim 4
Dependent Claim
9 words
counting successive pulse positions in which no pulses occur;
Claim 5
Dependent Claim
165 words
A zero suppression circuit comprising: a counter, a flip-flop circuit, a source of a data pulse stream, means responsive to said data pulse stream for initiaLly resetting said counter and said flip-flop each time a second pulse appears within N successive pulse positions in said data stream, means for resetting said counter each time a pulse appears in any one of the first N pulse positions of said data stream after said initial resetting, means for setting said flip-flop after the first pulse appearing in said stream in the next (N-2) pulse positions following a count of N in said counter, means for setting said counter to a count of (N-1) and resetting said flip-flop after (N-1) pulse positions following said count of N and including no more than one pulse; and means for forcing a pulse into the (N-1)st pulse position following said count of N in said counter if no pulse occurs in the next (N-2) pulse positions preceding unit (N-1)st pulse position.
Claim 6
Dependent Claim
165 words
A zero suppression circuit comprising: a counter, a flip-flop circuit, a source of a data pulse stream, means responsive to said data pulse stream for initiaLly resetting said counter and said flip-flop each time a second pulse appears within N successive pulse positions in said data stream, means for resetting said counter each time a pulse appears in any one of the first N pulse positions of said data stream after said initial resetting, means for setting said flip-flop after the first pulse appearing in said stream in the next (N-2) pulse positions following a count of N in said counter, means for setting said counter to a count of (N-1) and resetting said flip-flop after (N-1) pulse positions following said count of N and including no more than one pulse; and means for forcing a pulse into the (N-1)st pulse position following said count of N in said counter if no pulse occurs in the next (N-2) pulse positions preceding unit (N-1)st pulse position.
Claim 7
Dependent Claim
76 words
A zero suppression circuit for serial pulse data comprising: a pulse position counter, means for forcing a pulse into said serial pulse data to provide at least one pulse in each group of N or less pulse positions for at least one possible division of said pulse stream into such groups, and means for delaying said pulse forcing means to the end of a group of 2N pulse positions whenever consistent with the abovestated forcing criteria.
Claim 8
Dependent Claim
76 words
A zero suppression circuit for serial pulse data comprising: a pulse position counter, means for forcing a pulse into said serial pulse data to provide at least one pulse in each group of N or less pulse positions for at least one possible division of said pulse stream into such groups, and means for delaying said pulse forcing means to the end of a group of 2N pulse positions whenever consistent with the abovestated forcing criteria.
Claim 9
Dependent Claim
23 words
The zero suppression circuit according to claim 2 wherein said counter comprises a binary counter and said delaying means comprises a bistable circuit.
Claim 10
Dependent Claim
28 words
when said pulse count is zero, forcing a pulse in the last pulse position of said next group of N successive pulse positions and returning to step (2);
Claim 11
Dependent Claim
28 words
when said pulse count is zero, forcing a pulse in the last pulse position of said next group of N successive pulse positions and returning to step (2);
Claim 12
Dependent Claim
21 words
delaying said pulse forcing to the end of a group of 2N pulse positions whenever consistent with the above-stated forcing criteria.
Claim 13
Dependent Claim
21 words
delaying said pulse forcing to the end of a group of 2N pulse positions whenever consistent with the above-stated forcing criteria.
Claim 14
Dependent Claim
28 words
avoiding pulse forcing in a framing pulse position by forcing a pulse in the preceding pulse position whenever forcing would otherwise be necessary in said framing pulse position.
Claim 15
Dependent Claim
28 words
avoiding pulse forcing in a framing pulse position by forcing a pulse in the preceding pulse position whenever forcing would otherwise be necessary in said framing pulse position.
Claim 16
Dependent Claim
26 words
when said pulse count is one, omitting to force a pulse in said next group of N successive pulse positions, and returning to step (2); and
Claim 17
Dependent Claim
26 words
when said pulse count is one, omitting to force a pulse in said next group of N successive pulse positions, and returning to step (2); and
Claim 18
Dependent Claim
12 words
The zero suppression circuit according to claim 3 wherein N is eight.
Claim 19
Dependent Claim
38 words
The method according to claim 2 further including means for avoiding pulse forcing in a framing pulse position by forcing a pulse in the preceding pulse position whenever forcing would otherwise be necessary in said framing pulse position.
Claim 20
Dependent Claim
21 words
when said pulse count is two, returning to step (1) on the next succeeding pulse position in which no pulse occurs.
Claim 21
Dependent Claim
21 words
when said pulse count is two, returning to step (1) on the next succeeding pulse position in which no pulse occurs.
Claim 22
Independent Claim
49 words
The method of forcing a minimum number of pulses into a binary pulse train to maintain a preselected global pulse density ratio of 1/N and a local pulse density of at least one pulse in each group of N or less pulse positions, said method comprising the steps of:
Claim 23
Independent Claim
49 words
The method of forcing a minimum number of pulses into a binary pulse train to maintain a preselected global pulse density ratio of 1/N and a local pulse density of at least one pulse in each group of N or less pulse positions, said method comprising the steps of:
Claim 24
Independent Claim
15 words
The method of suppressing ZEROs in a stream of pulse positions comprising the steps of:
Claim 25
Independent Claim
15 words
The method of suppressing ZEROs in a stream of pulse positions comprising the steps of:
Claim 26
Dependent Claim
13 words
The method of suppressing ZEROs according to claim 7 wherein N is eight.
Claim 27
Dependent Claim
14 words
The method of suppressing ZEROs according to claim 7 further including the step of:
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-01 | 1979-06-02 | 1979-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-01 | 1983-06-02 | 1983-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-01 | 1987-06-02 | 1987-12-02 | $7700.00 | Window Closed / Lapsed |