Patent US3922844A successfully refreshed from Google Patents.
US3922844A
Expired / Lapsed
US
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Electronic timepiece
Assignee: Suwa Seikosha KK
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Filing: 1974-04-25
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Granted: 1975-12-02
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Expires: 1994-04-25
Abstract
Abstract An electronic timepiece, having an oscillator circuit producing a high frequency time standard signal and a divider circuit formed from a plurality of series-connected divider stages for producing low frequency timekeeping signals in response to said time standard signal, is provided with an adjusting circuit adapted to set each divider stage to thereby adjust the timekeeping signal produced thereby. The adjusting circuit allows a setting signal from a memory circuit to be applied to each divider stage through gate circuits at the beginning of the period of said timekeeping signal to thereby correct the timekeeping signal.
Inventors
- 👤 Motoyoshi Sakamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:16
CPC Classifications
G; G04; G04G; G04G3/00; G04G3/02; G04G3/022
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
152 words
In an electronic timepiece including an oscillator circuit producing a high frequency time standard signal, divider means including a plurality of series-connected divider stage counters for receiving said high frequency time standard signal and dividing same to produce a low frequency timekeeping signal of a frequency having a period which is different than the actual time sought to be counted thereby, the improvement comprising timekeeping signal adjusting means coupled by output means to each divider stage counter, said adjusting means including memory means, said adjusting means being responsive to said timekeeping signal for supplying setting signals to predetermined divider stage counters through said output means selected by said memory means at the beginning of each period of said timekeeping signal to reset the count of each of said divider stage counters having setting signals applied thereto to adjust the period of said timekeeping signal to the actual time sought to be counted.
Claim 2
Dependent Claim
152 words
In an electronic timepiece including an oscillator circuit producing a high frequency time standard signal, divider means including a plurality of series-connected divider stage counters for receiving said high frequency time standard signal and dividing same to produce a low frequency timekeeping signal of a frequency having a period which is different than the actual time sought to be counted thereby, the improvement comprising timekeeping signal adjusting means coupled by output means to each divider stage counter, said adjusting means including memory means, said adjusting means being responsive to said timekeeping signal for supplying setting signals to predetermined divider stage counters through said output means selected by said memory means at the beginning of each period of said timekeeping signal to reset the count of each of said divider stage counters having setting signals applied thereto to adjust the period of said timekeeping signal to the actual time sought to be counted.
Claim 3
Dependent Claim
71 words
An electronic timepiece as claimed in claim 1, wherein said output means includes a gating circuit coupled to said memory means and to each of said binary divider stage counters, said memory means effecting the setting of said gating circuit so that same in response to the beginning of each period of said timekeeping signal effects a predetermined gating of said setting signals to each of said predetermined divider stage counters.
Claim 4
Dependent Claim
41 words
An electronic timepiece as claimed in claim 2, wherein said adjusting means further includes a pulse generating circuit for receiving said timekeeping signal and in response thereto applying a pulse to said gating circuit once each period of said timekeeping signal.
Claim 5
Dependent Claim
33 words
An electronic timepiece as claimed in claim 3, wherein said setting signals set to one each of said predetermined divider stage counters selected at the beginning of each period of said timekeeping signal.
Claim 6
Dependent Claim
55 words
An electronic timepiece as claimed in claim 4, wherein said divider means is adapted to count in an addition mode, the state of each divider stage counter when counting in an opposite mode for a period corresponding to actual time determining the predetermined counters to which said setting signals are applied by said memory means.
Claim 7
Dependent Claim
157 words
An electronic timepiece as claimed in claim 3, wherein said memory means includes a second gating circuit having applied thereto a referEnce signal corresponding to the actual period which it is desired to adjust the time-keeping signal to, said memory means further including a memory divider circuit having the same number of divider stage counters as said divider circuit, said memory divider stage counters being set to count in the opposite counting mode from the divider stage counters of said divider circuit, said memory gating circuit being adapted to apply said high frequency standard signal to said memory divider circuit for the period determined by said reference signal, the state of each of said memory divider stage counters at the end of said period determined by said reference signal automatically predetermining the setting of said gating circuit to determine the stage counters having setting signals applied thereto at the beginning of each period of said time-keeping signal.
Claim 8
Dependent Claim
33 words
An electronic timepiece as claimed in claim 3, wherein said setting signals reset to zero each of said predetermined divider stage counters selected at the beginning of each period of said timekeeping signal.
Claim 9
Dependent Claim
55 words
An electronic timepiece as claimed in claim 7, wherein said divider means is adapted to count in an addition mode, the state of each divider stage counter when counting in an opposite mode for a period corresponding to actual time determining the predetermined counters to which said setting signals are applied by said memory means.
Claim 10
Dependent Claim
55 words
An electronic timepiece as claimed in claim 4, wherein said divider means is adapted to count in a subtraction mode, the state of each divider stage counter when counting in an opposite mode for a period corresponding to actual time determining the predetermined counters to which said setting signals are applied by said memory means.
Claim 11
Dependent Claim
55 words
An electronic timepiece as claimed in claim 7, wherein said divider means is adapted to count in a subtraction mode, the state of each divider stage counter when counting in an opposite mode for a period corresponding to actual time determining the predetermined counters to which said setting signals are applied by said memory means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-01 | 1979-06-02 | 1979-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-01 | 1983-06-02 | 1983-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-01 | 1987-06-02 | 1987-12-02 | $7700.00 | Window Closed / Lapsed |