Signal level displaying apparatus

Claim 2

A signal level displaying apparatus comprising: plasma display means having a plurality of channel electrode parts provided respectively for channels to be level-displayed, a plurality of level electrode parts disposed respectively in correspondence to said channel electrode parts, a glass enclosure accommodating said channel electrode parts and said level electrode parts, and a gas mixture filled in said glass enclosure, each of said level electrode parts comprising a plurality of level electrodes disposed in order of the signal level of the corresponding channel; first display pulse supplying means for supplying a first display pulse signal to be applied to the level electrode parts of said plasma display means; second display pulse supplying means for supplying a second display pulse signal to be applied to the channel electrode parts of said plasma means, the polarity of the second display pulse signal being opposite to the polarity of the first display pulse signal; control pulse supplying means for supplying control pulse signals for time division; channel signal time division means for time-dividing a plurality of input channel signals in accordance with the control pulse signals from said control pulse supplying means thereby to pass selectively channel signals with time-division time zones which differ successively; a plurality of level selection circuit means each having successively differing threshold values, each of said level selection circuit means responsive to the output signal of said channel signal time division means for producing a low voltage signal when the level of the output signal of said channel signal time division means is higher than its own threshold value and for producing a high voltage signal when the signal of the output signal of said channel signal time division means is lower than its own threshold value; a plurality of level electrode selection circuit means respectively connected to the corresponding level selection circuit means, the outputs of said level electrode selection circuit means being respectively connected to the corresponding level electrodes of the level electrode parts, each of the level electrode selection circuit means supplying the first display pulse signal from said first display pulse supplying means to the corresponding level electrodes in response to said low voltage signal and suppressing the first display pulse signal in response to said high voltage signal; and channel electrode selection means operating in accordance with the control pulse signaLs from said control pulse supplying means to time-divide the second display pulse signal from said second display supplying means in synchronism with said channel signal time division means and to supply the resulting time divided pulses with successively differing time division zones to all of said channel electrode parts of said plasma display means.

Claim 3

The signal level displaying apparatus as claimed in claim 1 in which said control pulse supplying means comprises a quaternary decoder which produces as an output four kinds of control pulses having parts of different levels in successively differing time zones; and in which the input channel signals entering said channel signal time division means comprise four-channel signals; and in which said channel electrode parts of said plasma display means comprise electrode parts for four channels disposed with specific relationships respectively for the four channels.

Claim 4

A signal level displaying apparatus comprising: plasma display means having a plurality of channel electrode parts provided respectively for channels to be level-displayed, a plurality of level electrode parts disposed respectively in correspondence to said channel electrode parts, a glass enclosure accommodating said channel electrode parts and said level electrode parts, and a gas mixture filled in said glass enclosure, each of said level electrode parts comprising a plurality of level electrodes disposed in order of the signal level of the corresponding channel; first display pulse supplying means for supplying a first display pulse signal to be applied to the level electrode parts of said plasma display means; second display pulse supplying means for supplying a second display pulse signal to be applied to the channel electrode parts of said plasma display means, the polarity of the second pulse signal being opposite to the polarity of the first pulse signal; control pulse supplying means for supplying control pulse signals for time division; first channel signal time division means for time-dividing a plurality of input channel signals in accordance with the control pulse signals from said control pulse supplying means thereby to pass selectively channel signals with the time-division time zones which differ successively; a plurality of first level selection circuit means each having successively differing threshold values, each of said first level selection circuit means responsive to the output signal of said first channel signal time division means for producing a low voltage signal when the level of the output signal of said first channel signal time division means is higher than its own threshold value and for producing a high voltage signal when the level of the output signal of said first channel signal time division means is lower than its own threshold value; a plurality of memorizing means for respectively memorizing the maximum value of the level of a corresponding input channel signal; second channel signal time division means for time-dividing the output signals of said memorizing means in accordance with the control pulse signals from said control pulse supplying means thereby to pass selectively the output signals of said memorizing means with time-division time zones which differ successively; a plurality of second level selection circuit means each having successively differing threshold values, each of said second level selection circuit means responsive to the output signal of said second signal time division means for producing a low voltage signal when the level of the output signal of said second channel signal time division means is higher than its own threshold value and for producing a high voltage signal when the level of the output signal of said second channel signal time division means is lower than its own threshold value; display designation logic circuit means comprising a plurality of input terminals, each of which receives the output signal of a corresponding second level selEction circuit means, a plurality of inverter means for respectively inverting the signal from the corresponding input terminal, and a plurality of NAND circuit means for respectively producing a NAND product of the output signal of the corresponding inverter means and the signal from the input terminal which receives the output signal of the second level selection circuit means having the adjacently lower threshold value than the threshold value of the corresponding second level circuit means, and a plurality of output terminals for respectively receiving the output signal of the corresponding NAND circuit means; a plurality of level electrode selection circuit means respectively connected to the corresponding first level selection circuit means and the corresponding output terminal of said display designation logic circuit means, the outputs of said level electrode selection circuit means being respectively connected to the corresponding level electrodes of said level electrode parts, each of the level electrode selection circuit means for supplying the first display pulse signal from said first display pulse supplying means to the corresponding level electrodes in response to said low voltage signal and for suppressing the first display pulse signal in response to said high voltage signal; and channel electrode selection means operating in accordance with the control pulse signals from said control pulse supplying means to time-divide the second display pulse signal from said second display pulse supplying means in synchronism with the first and second channel signal time division means and to supply the resulting time-divided pulses with successively differing time division zones to all of the channel electrode parts of said plasma display means.

Claim 5

A signal level displaying apparatus comprising: plasma display means having a plurality of channel electrode parts provided respectively for channels to be level-displayed, a plurality of level electrode parts disposed respectively in correspondence to said channel electrode parts, a glass enclosure accommodating said channel electrode parts and said level electrode parts, and a gas mixture filled in said glass enclosure, each of said level electrode parts comprising a plurality of level electrodes disposed in order of the signal level of the corresponding channel; first display pulse supplying means for supplying a first display pulse signal to be applied to the level electrode parts of said plasma display means; second display pulse supplying means for supplying a second display pulse signal to be applied to the channel electrode parts of said plasma display means, the polarity of the second pulse signal being opposite to the polarity of the first pulse signal; control pulse supplying means for supplying control pulse signals for time division; first channel signal time division means for time-dividing a plurality of input channel signals in accordance with the control pulse signals from said control pulse supplying means thereby to pass selectively channel signals with the time-division time zones which differ successively; a plurality of first level selection circuit means each having successively differing threshold values, each of said first level selection circuit means responsive to the output signal of said first channel signal time division means for producing a low voltage signal when the level of the output signal of said first channel signal time division means is higher than its own threshold value and for producing a high voltage signal when the level of the output signal of said first channel signal time division means is lower than its own threshold value; a plurality of memorizing means for respectively memorizing the maximum value of the level of a corresponding input channel signal; second channel signal time division means for time-dividing the output signals of said memorizing means in accordance with the control pulse signals from said control pulse supplying means thereby to pass selectively the output signals of said memorizing means with time-division time zones which differ successively; a plurality of second level selection circuit means each having successively differing threshold values, each of said second level selection circuit means responsive to the output signal of said second signal time division means for producing a low voltage signal when the level of the output signal of said second channel signal time division means is higher than its own threshold value and for producing a high voltage signal when the level of the output signal of said second channel signal time division means is lower than its own threshold value; display designation logic circuit means comprising a plurality of input terminals, each of which receives the output signal of a corresponding second level selEction circuit means, a plurality of inverter means for respectively inverting the signal from the corresponding input terminal, and a plurality of NAND circuit means for respectively producing a NAND product of the output signal of the corresponding inverter means and the signal from the input terminal which receives the output signal of the second level selection circuit means having the adjacently lower threshold value than the threshold value of the corresponding second level circuit means, and a plurality of output terminals for respectively receiving the output signal of the corresponding NAND circuit means; a plurality of level electrode selection circuit means respectively connected to the corresponding first level selection circuit means and the corresponding output terminal of said display designation logic circuit means, the outputs of said level electrode selection circuit means being respectively connected to the corresponding level electrodes of said level electrode parts, each of the level electrode selection circuit means for supplying the first display pulse signal from said first display pulse supplying means to the corresponding level electrodes in response to said low voltage signal and for suppressing the first display pulse signal in response to said high voltage signal; and channel electrode selection means operating in accordance with the control pulse signals from said control pulse supplying means to time-divide the second display pulse signal from said second display pulse supplying means in synchronism with the first and second channel signal time division means and to supply the resulting time-divided pulses with successively differing time division zones to all of the channel electrode parts of said plasma display means.