Scan operation for a central processor

Claim 2

In a central processor of the type which controls the operation of telephone exchange subsystems to establish requested service between telephone subscribers in response to a plurality of addressable multiplE bit operational codes, wherein each of the subsystems is connected to the central processor by a common data bus and assigned a discrete subsystem address for enabling the addressing of each subsystem and wherein one of the subsystems is a program memory containing the plurality of operational codes, the improvement of scan means responsive to a particular operational code which includes a first partial subsystem address for interrogating preselected subsystems to locate stored subsystem data which contains preselected bits of data comprising: an instruction register for storing the particular operational code; an instruction register byte selector coupled to said instruction register for selecting said first partial subsystem address; a first accumulator for storing a second partial subsystem address; combining means coupled to said instruction register byte selector and said first accumulator for combining said first and second partial subsystem addresses to provide a composite subsystem address; a bus address register coupled to said combining means and to said common data bus for addressing the subsystem having said composite subsystem address for causing it to transmit the data stored therein over said common data bus; a second accumulator for storing the preselected bits of data as a compare constant; a comparator coupled to said common data bus and to said second accumulator for comparing said transmitted data to said compare constant for determining if said transmitted data and said compare constant are identical; and means responsive to said comparator for providing a first control signal when said transmitted data and said compare constant are identical and for providing a second control signal when said transmitted data and said compare constant are not identical.

Claim 3

A central processor in accordance with claim 1 further comprising a third accumulator for storing a mask constant and masking means coupled to said common data bus and to said third accumulator for masking said transmitted data with said mask constant for transforming said transmitted data into a data work having predetermined bits to be compared to said compare constant by said comparator.

Claim 4

A central processor in accordance with claim 2 further comprising a fourth accumulator coupled to said combining means for storing an increment address constant, and wherein said combining means combines said second partial subsystem address with said increment address constant responsive to said second control signal to provide sequential incremented composite subsystem addresses as long as said masked transmitted data and said compare constant are not identical.

Claim 5

A central processor in accordance with claim 3 wherein said fourth accumulator additionally includes a down counter for initially storing a cycle data word representing a predetermined number of subsystem address increments and means responsive to said second control signal for decrementing said down counter.

Claim 6

A central processor in accordance with claim 4 further comprising a program address register for sequentially storing the address of the next program memory operational code and means coupled to said program address register and responsive to said down counter for terminating the scan means and for causing said program address register to pass over the next operational code when said down counter is decremented by said predetermined number.

Claim 7

A central processor in accordance with claim 5 further comprising means responsive to said first control signal and coupled to said program address register for causing said program address register to initiate the next operational code in response to said first control signal.

Claim 8

A central processor in accordance with claim 5 further comprising means responsive to said second control signal and coupled to said program address register for causing said program address register to initiate the next operational code in response to said second coNtrol signal.

Claim 9

A central processor in accordance with claim 3 wherein said incremented composite subsystem address and said composite subsystem address comprise twenty bits, wherein said first partial subsystem address comprises four bits and wherein said second partial subsystem address comprises sixteen bits.

Claim 10

In a central processor of the type which controls the operation of telephone exchange subsystems to establish requested service between telephone subscribers in response to a plurality of addressable multiple bit operational codes, wherein each of the subsystems is connected to the central processor by a common data bus and assigned a discrete subsystem address for enabling the addressing of each subsystem and wherein one of the subsystems is a program memory containing the plurality of operational codes, the improvement of a scan means responsive to a particular operational code which includes a mode bit and first and second partial subsystem addresses for interrogating preselected subsystems to locate stored subsystem data which contains preselected bits of data comprising: an instruction register for storing the particular operational code; an instruction register byte selector coupled to said instruction register for selecting said first and second partial subsystem addresses; a first accumulator for storing a third partial subsystem address; combining means coupled to said instruction register byte selector and said first accumulator for combining said first and third partial subsystem addresses to provide an address word obtaining composite subsystem address; a bus address register coupled to said combining means and to said common data bus and responsive to said combining means for addressing the subsystem having said address word obtaining composite subsystem address for causing it to transmit the address word stored therein over said common data bus; said combining means additionally being coupled to said common data bus and responsive to said mode bit for combining said second partial subsystem address with said address word for providing a data obtaining composite sybsystem address; said bus address register additionally being responsive to said data obtaining composite subsystem address for addressing the subsystem having said data obtaining composite address for causing it to transmit the data stored therein over said common data bus; a second accumulator for storing the preselected bits of data as a compare constant; a comparator coupled to said common data bus and to said second accumulator for comparing said transmitted data to said compare constant for determining if said transmitted data and said compare constant are identical; and means responsive to said comparator for providing a first control signal when said transmitted data and said compare constant are identical and for providing a second control signal when said transmitted data and said compare constant are not identical.

Claim 11

In a central processor of the type which controls the operation of telephone exchange subsystems to establish requested service between telephone subscribers in response to a plurality of addressable multiple bit operational codes, wherein each of the subsystems is connected to the central processor by a common data bus and assigned a discrete subsystem address for enabling the addressing of each subsystem and wherein one of the subsystems is a program memory containing the plurality of operational codes, the improvement of a scan means responsive to a particular operational code which includes a mode bit and first and second partial subsystem addresses for interrogating preselected subsystems to locate stored subsystem data which contains preselected bits of data comprising: an instruction register for storing the particular operational code; an instruction register byte selector coupled to said instruction register for selecting said first and second partial subsystem addresses; a first accumulator for storing a third partial subsystem address; combining means coupled to said instruction register byte selector and said first accumulator for combining said first and third partial subsystem addresses to provide an address word obtaining composite subsystem address; a bus address register coupled to said combining means and to said common data bus and responsive to said combining means for addressing the subsystem having said address word obtaining composite subsystem address for causing it to transmit the address word stored therein over said common data bus; said combining means additionally being coupled to said common data bus and responsive to said mode bit for combining said second partial subsystem address with said address word for providing a data obtaining composite sybsystem address; said bus address register additionally being responsive to said data obtaining composite subsystem address for addressing the subsystem having said data obtaining composite address for causing it to transmit the data stored therein over said common data bus; a second accumulator for storing the preselected bits of data as a compare constant; a comparator coupled to said common data bus and to said second accumulator for comparing said transmitted data to said compare constant for determining if said transmitted data and said compare constant are identical; and means responsive to said comparator for providing a first control signal when said transmitted data and said compare constant are identical and for providing a second control signal when said transmitted data and said compare constant are not identical.

Claim 12

A central processor in accordance with claim 9 further comprising a third accumulator for storing a mask constant and masking means coupled to said common data bus and to said third accumulator for masking said transmitted data with said mask constant for transforming said transmitted data into a data word having predetermined bits to be compared to said compare constant by said comparator.

Claim 13

A central processor in accordance with claim 10 further comprising a fourth accumulator coupled to said combining means for storing an increment address constant, and wherein said combining means combines said third partial subsystem address with said increment address constant responsive to said second control signal to provide sequential data obtaining incremented composite subsystem addresses as long as said masked transmitted data and said compare constant are not identical.

Claim 14

A central processor in accordance with claim 11 wherein said fourth accumulator additionally includes a down counter for initially storinG a cycle data word representing a predetermined number of subsystem data obtaining address increments and means responsive to said second control signal for decrementing said down counter.

Claim 15

A central processor in accordance with claim 12 further comprising a program address register for sequentially storing the address of the next program memory operational code and means coupled to said program address register and responsive to said down counter for terminating the scan means and for causing said program address register to pass over the next operational code when said down counter is decremented by said predetermined number.

Claim 16

A central processor in accordance with claim 13 further comprising means responsive to said first control signal and coupled to said program address register for causing said program address register to initiate the next operational code in response to said first control signal.

Claim 17

A central processor in accordance with claim 13 further comprising means responsive to said control signal and coupled to said program address register for causing said program address register to initiate the next operational code in response to said second control signal.

Claim 18

A central processor in accordance with claim 11 wherein said address word obtaining composite subsystem address, said incremented data obtaining composite subsystem address and said data obtaining composite subsystem address comprise twenty bits, wherein said first and second partial subsystem address comprises four bits and wherein said third partial subsystem address comprises sixteen bits.