US3922643A
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Memory and memory addressing system
Assignee: General Dynamics Government Systems Corp
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Filing: 1974-09-04
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Granted: 1975-11-25
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Expires: 1994-09-04
Abstract
Abstract Memory system employed in a time compression scanner for monitoring telephone lines. Digital samples are written into the storage locations of a memory during one memory addressing period, and these samples are read out during the next memory addressing period, but in a different order from the order in which they were entered. As each sample is read out, it is replaced by a new sample which is to be read out during the subsequent memory addressing period. The memory address for writing in and reading out each sample is controlled by a series of flip-flops. Clock pulses are directed to a different one of the flip-flops during each memory addressing period in a recurring sequence of addressing periods in order to cause the storage locations to be addressed in a different order during each memory addressing period.
Inventors
- 👤 Margaret A Poole
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:58
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F7/785; G11; G11C; G11C7/00; G11C7/16; G11C8/00; H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/457
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
222 words
Memory system in which word storage locations are addressed in different order during each address period in a recurring sequence of address periods including memory means having 2N M word storage locations, wherein N and M are each integers, said memory means having N+M address inputs; N+M flip-flop means arranged in order each having an address output connected to a different one of the address inputs of the memory means and each having a clock input connection; each flip-flop means having an output connection coupled to the clock input connection of the next flip-flop means in the order, with the output connection of the last flip-flop means in the order being coupled to the clock input connection of the first flip-flop means in the order; a source of periodic clock pulses; a plurality of gating means each being connected between said source of periodic clock pulses and the clock input connection of a different one of said flip-flop means; and control means for activating each of said gating means in a recurring sequence to permit the passage of clock pulses therethrough to its associated flip-flop means, each gating means being activated for an address period of 2N M clock pulses, whereby the word storage locations are addressed in a different order during each address period of a recurring sequence of address periods.
Claim 2
Dependent Claim
222 words
Memory system in which word storage locations are addressed in different order during each address period in a recurring sequence of address periods including memory means having 2N M word storage locations, wherein N and M are each integers, said memory means having N+M address inputs; N+M flip-flop means arranged in order each having an address output connected to a different one of the address inputs of the memory means and each having a clock input connection; each flip-flop means having an output connection coupled to the clock input connection of the next flip-flop means in the order, with the output connection of the last flip-flop means in the order being coupled to the clock input connection of the first flip-flop means in the order; a source of periodic clock pulses; a plurality of gating means each being connected between said source of periodic clock pulses and the clock input connection of a different one of said flip-flop means; and control means for activating each of said gating means in a recurring sequence to permit the passage of clock pulses therethrough to its associated flip-flop means, each gating means being activated for an address period of 2N M clock pulses, whereby the word storage locations are addressed in a different order during each address period of a recurring sequence of address periods.
Claim 3
Dependent Claim
80 words
A memory system in accordance with claim 1 wherein said control means activates said gating means in a recurring sequence causing the gating means to permit the first flip-flop means in the order to receive clock pulses during the first address period of each sequence, and during each subsequent address period of the sequence to permit the Mth flip-flop Means in recirculating order from the flip-flop means which received clock pulses during the preceding address period to receive clock pulses.
Claim 4
Dependent Claim
90 words
A memory system in accordance with claim 2 wherein said control means includes counter means coupled to said source of periodic clock pulses and operable to produce a different combination of output signals during each address period of a recurring sequence of address periods; and decoder means connected to the counter means and to the gating means and being operable to activate a different one of the gating means during each address period of a recurring sequence of address periods as determined by the output signals from the counter means.
Claim 5
Dependent Claim
38 words
A memory system in accordance with claim 3 including reset means coupled between the counter means and the flip-flop means and operable upon completion of each address period to reset all the flip-flop means to an initial state.
Claim 6
Dependent Claim
150 words
A memory system in accordance with claim 4 wherein each of said gating means includes a coupling gate connected between the clock input connection of its associated flip-flop means and the output connection of the preceding flip-flop means in the order, the coupling gate associated with the first flip-flop means in the order being connected to the output connection of the last flip-flop means in the order, each of said coupling gates being connected to said decoder means; and said decoder means when activating a gating means being operable to prevent the coupling gate of that gating means from passing signals from the output connection to the clock input connection to which it is connected, and when not activating a gating means being operable to permit the coupling gate of that gating means to pass signals from the output connection to the clock input connection to which it is connected.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-24 | 1979-05-26 | 1979-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-24 | 1983-05-26 | 1983-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-24 | 1987-05-26 | 1987-11-25 | $7700.00 | Window Closed / Lapsed |