Distributing and collecting memory array and transfer system

Claim 2

Buffering apparatus for transferring signal bits of digital information to a plurality of first bit-serial channels from at least one second bit-parallel channel, the apparatus comprising: a memory comprising a matrix of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel; a separate input conductor for each said column, the input conductors together receiving signal bits from the bit-parallel channel; a separate output conductor for each row, each for coupling signal bits to one of said bit-serial channels; first gating means establishing a parallel bit transfer path from all input conductors to the corresponding column cells in any one row; and second gating means establishing a path for transferring bits of information from all cells in any row to the corresponding output conductor including serial gating means for establishing such path serial by cell within each row.

Claim 3

Apparatus according to claim 1 wherein the second gating means comprises means for simultaneously transferring a bit from a cell in each row in parallel.

Claim 4

Apparatus according to claim 1 wherein said cells are in groups, a cell from each row in each group, and comprising group transfer means for simultaneously enabling the serial gating means to simultaneousLy transfer a bit from a cell in each group to one of the output conductors.

Claim 5

Apparatus according to claim 3 comprising means for enabling said group transfer means to transfer bits serially by groups.

Claim 6

Apparatus according to claim 4 wherein said enabling means comprises a counter for repeatedly counting through a sequence of counts, one count for each of said groups.

Claim 7

Buffering apparatus for transferring signal bits of digital information between a plurality of first bit-serial channels and at least one second bit-parallel channel, the apparatus comprising: a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel, each of said pairs of cells comprising first and second cells; first means establishing a parallel bit transfer path between the second channel and all cells in any one row, said first means comprising means for establishing transfer paths into the first cells from the second channel and means for establishing transfer paths out of the second cells to the second channel; and second means establishing a path adapted for transferring bits of information serially between all cells in a row and the corresponding first channel.

Claim 8

Buffering apparatus for transferring signal bits of digital information between a plurality of first bit-serial channels and at least one second bit-parallel channel, the apparatus comprising: a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel, each of said pairs of cells comprising first and second cells; first means establishing a parallel bit transfer path between the second channel and all cells in any one row, said first means comprising means for establishing transfer paths into the first cells from the second channel and means for establishing transfer paths out of the second cells to the second channel; and second means establishing a path adapted for transferring bits of information serially between all cells in a row and the corresponding first channel.

Claim 9

Buffering apparatus for transferring signal bits of digital information between a plurality of first bit-serial channels and at least one second bit-parallel channel, the apparatus comprising: a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel, each of said pairs of cells comprising first and second cells; first means establishing a parallel bit transfer path between the second channel and all cells in any one row; and second means establishing a path adapted for transferring bits of information serially between all cells in a row and the corresponding first channel, said second means establishing transfer paths into the second cells from the corresponding first channels and establishing transfer paths out of the first cells to the second channels.

Claim 10

Buffering apparatus for transferring signal bits of digital information between a plurality of first bit-serial channels and at least one second bit-parallel channel, the apparatus comprising: a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel, each of said pairs of cells comprising first and second cells; first means establishing a parallel bit transfer path between the second channel and all cells in any one row; and second means establishing a path adapted for transferring bits of information serially between all cells in a row and the corresponding first channel, said second means establishing transfer paths into the second cells from the corresponding first channels and establishing transfer paths out of the first cells to the second channels.

Claim 11

Buffering apparatus for transferring signal bits of digital information between a plurality of first bit-serial channels and at least one second bit-parallel channel, the apparatus comprising: a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel, each of said pairs of cells comprising first and second cells; first means establishing a parallel bit transfer path between the second channel and all cells in any one row, said first means comprising means establishing transfer paths into the first cells from the second channel and means establishing transfer paths out of the second cells to the second channel; and second means establishing a path adapted for transferring bits of information serially between all cells in a row and the corresponding first channel, said second means comprising means establishing transfer paths into the second cells from the corresponding first channels and means establishing transfer paths out of the first cells to the corresponding first channels.

Claim 12

Buffering apparatus for transferring signal bits of digital information between a plurality of first bit-serial channels and at least one second bit-parallel channel, the apparatus comprising: a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel, each of said pairs of cells comprising first and second cells; first means establishing a parallel bit transfer path between the second channel and all cells in any one row, said first means comprising means establishing transfer paths into the first cells from the second channel and means establishing transfer paths out of the second cells to the second channel; and second means establishing a path adapted for transferring bits of information serially between all cells in a row and the corresponding first channel, said second means comprising means establishing transfer paths into the second cells from the corresponding first channels and means establishing transfer paths out of the first cells to the corresponding first channels.

Claim 13

Buffering apparatus for transferring signal bits of digital information between a plurality of first bit-serial channels and at least one second bit-parallel channel, the apparatus comprising: a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel; first means establishing a parallel bit transfer path between the second channel and all cells in any one row, said first means comprising means for addressing any row and means for simultaneously transferring bits between the cells in the addressed row and the second channel; and second means establishing a path adapted for transferring bits of information serially between all cells in a row and the first channel corresponding to the row.

Claim 14

Buffering apparatus for transferring signal bits of digital information between a plurality of first bit-serial channels and at least one second bit-parallel channel, the apparatus comprising: a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel; first means establishing a parallel bit transfer path between the second channel and all cells in any one row, said first means comprising means for addressing any row and means for simultaneously transferring bits between the cells in the addressed row and the second channel; and second means establishing a path adapted for transferring bits of information serially between all cells in a row and the first channel corresponding to the row.

Claim 15

Buffering apparatus for transferring signal bits of digital information between a plurality of first bit-serial channels and at least one second bit-parallel channel, the apparatus comprising: a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel; first means establishing a parallel bit transfer path between the second channel and all cells in any one row; and second means establishing a path adapted for transferring bits of information serially between all cells in a row and the corresponding first channel, said second means comprising means for simultaneously addressing a different cell in each row, and means for transferring bits between the addressed cells and the first channel corresponding to the row from which a bit is transferred.

Claim 16

Buffering apparatus for transferring signal bits of digital information between a plurality of first bit-serial channels and at least one second bit-parallel channel, the apparatus comprising: a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each first channel; first means establishing a parallel bit transfer path between the second channel and all cells in any one row; and second means establishing a path adapted for transferring bits of information serially between all cells in a row and the corresponding first channel, said second means comprising means for simultaneously addressing a different cell in each row, and means for transferring bits between the addressed cells and the first channel corresponding to the row from which a bit is transferred.

Claim 17

Buffering apparatus for bidirectionally transferring bit signals representing digital information between a unit transferring signals parallel by bit and any one of a plurality of units transferring signals serial by bit, the combination comprising: a memory comprising a matrix of bit storing cells connected in multiple rows and multiple columns; at least one conductor for each of said columns; bidirectional parallel gating means for coupling bit signals from each of said at least one conductors into the cells in the corresponding column and vice versa, said parallel gating means coupling said signals between all cells in any one row and said at least one conductors; at least one conductor for each of said rows; and bidirectional serial gating means for serially coupling bit signals from each row conductor into each cell in the corresponding row and vice versa.

Claim 18

Buffering apparatus for bidirectionally transferring bit signals representing digital information between a unit transferring signals parallel by bit and any one of a plurality of units transferring signals serial by bit, the combination comprising: a memory comprising a matrix of bit storing cells connected in multiple rows and multiple columns; at least one conductor for each of said columns; bidirectional parallel gating means for coupling bit signals from each of said at least one conductors into the cells in the corresponding column and vice versa, said parallel gating means coupling said signals between all cells in any one row and said at least one conductors; at least one conductor for each of said rows; and bidirectional serial gating means for serially coupling bit signals from each row conductor into each cell in the corresponding row and vice versa.

Claim 19

The apparatus of claim 11 comprising parallel addressing means for addressing any one of the rows of cells, the parallel gating means being responsive to the addressing means for bidirectionally coupling bit signals into and out of the addressed row of cells.

Claim 20

The apparatus of claim 11 comprising serial addressing means for serially addressing a series of groups of cells, each group comprising a cell from each row, said serial gating means being responsive to the serial addressing means for bidirectionally coupling the bit signals into and out of the addressed group of cells.

Claim 21

The apparatus of claim 11 wherein each of said cells in each row comprises a pair of first and second bit storing cells, said parallel addressing means comprising means for addressing any one of the rows of pairs of cells, said serial addressing means comprising means for serially addressing groups of pairs of cells, each group comprising a different pair of cells from each row, each of the at least one column and row conductors comprising separate input and output conductors, said bidirectional parallel gating means comprising input parallel gating means for establishing a bit transfer path from each input column conductor into the first cell of the corresponding column in any row and output parallel gating means for establishing a bit transfer path out of each second cell in any row to the output column conductor corresponding to the cell, said serial gating means comprising input serial gating means for establishing a bit transfer path from any of the input row conductors into any one of the second cells of the corresponding row and output serial gating means for establishing a bit transfer path to each output row conductor out of any one of the first cells in the corresponding row.

Claim 22

Serial-parallel bidirectional buffering apparatus comprising: a memory comprising a matrix of bit storing cells connected in multiple rows and multiple columns; conductor means for each row and conductor means for each column of cells; bidirectional parallel gating means for each row for establishing a parallel bit transfer path between the cells in the corresponding row and each column conductor means; and bidirectional serial gating means for each row condUctor comprising means for establishing a bit transfer path between the corresponding row conductor means and all cells in the corresponding row.

Claim 23

Serial-parallel bidirectional buffering apparatus comprising: a memory comprising a matrix of bit storing cells connected in multiple rows and multiple columns; conductor means for each row and conductor means for each column of cells; bidirectional parallel gating means for each row for establishing a parallel bit transfer path between the cells in the corresponding row and each column conductor means; and bidirectional serial gating means for each row condUctor comprising means for establishing a bit transfer path between the corresponding row conductor means and all cells in the corresponding row.

Claim 24

Serial-parallel buffering apparatus comprising: a matrix of bit storing cells connected in multiple rows and multiple columns, the cells being arranged into a plurality of groups, a different cell from each row in each group; conductor means for each row and conductor means for each column of cells; parallel addressing means for addressing each row; serial addressing means for serially addressing each group of cells; parallel gating means for each row responsive to the parallel addressing means for establishing a parallel bit transfer path between the addressed row of cells and each column conductor means; and serial gating means for each row conductor means responsive to the serial addressing means for establishing a bit transfer path between the cell in the addressed group of the corresponding row and the corresponding row conductor means.

Claim 25

Serial-parallel buffering apparatus comprising: a matrix of bit storing cells connected in multiple rows and multiple columns, the cells being arranged into a plurality of groups, a different cell from each row in each group; conductor means for each row and conductor means for each column of cells; parallel addressing means for addressing each row; serial addressing means for serially addressing each group of cells; parallel gating means for each row responsive to the parallel addressing means for establishing a parallel bit transfer path between the addressed row of cells and each column conductor means; and serial gating means for each row conductor means responsive to the serial addressing means for establishing a bit transfer path between the cell in the addressed group of the corresponding row and the corresponding row conductor means.

Claim 26

Apparatus according to claim 16 wherein the cells in each group are from different columns.

Claim 27

Apparatus according to claim 16 wherein each of said cells comprises a pair of first and second cells and wherein said parallel gating means comprises input parallel gating means for each row for establishing a bit transfer path from each column conductor means into the first cells in the corresponding column of the addressed row and output parallel gating means for each row responsive to the parallel addressing means for establishing a bit transfer path out of the second cell of each column of the addressed row to the corresponding colun conductor means, and wherein said serial gating means comprises a serial input gating means responsive to the serial addressing means for establishing a bit transfer path from the row conductor means into the second cells of the corresponding row and output gating means responsive to the serial addressing means for establishing a bit transfer path out of the first cells to the row conductor means of the corresponding row.

Claim 28

Apparatus according to claim 16 wherein each of said bit storing cells comprises a pair of first and second cells, wherein said row conductor means comprises input and output conductors, wherein said parallel gating means comprises input parallel gating means for each row responsive to the parallel addressing means for establishing a bit transfer path from each column conductor means into the first cells in the corresponding column of the addressed row, and output parallel gating means for each row responsive to the parallel addressing means for establishing a bit transfer path out of the second cell of each column of the addressed row to the corresponding column conductor means; and wherein said serial gating means comprises a serial input gating means responsive to the serial addressing means for establishing a bit transfer path from the input row conductor means into the second cells of the corresponding row and output gating means responsive to the serial addressing means for establishing a bit transfer path out of the first cells to the output row conductor means of the corresponding row.

Claim 29

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means, said cells being in groups, a different cell from each row in each group; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row; and second transfer means for each row for establishing further parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means serially transfErring bits of information between all cells in a row and the corresponding second means, the second transfer means comprising means for simultaneously transferring a bit from a cell in each group along said further parallel paths.

Claim 30

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means, said cells being in groups, a different cell from each row in each group; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row; and second transfer means for each row for establishing further parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means serially transfErring bits of information between all cells in a row and the corresponding second means, the second transfer means comprising means for simultaneously transferring a bit from a cell in each group along said further parallel paths.

Claim 31

Apparatus according to claim 20 comprising means for enabling said group transfer means to transfer bits serially by group.

Claim 32

Apparatus according to claim 21 wherein said enabling means comprises a counting means for repeatedly counting through a sequence of counts, one count for each of said groups.

Claim 33

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means, each of said pairs of cells comprising first and second cells; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row, said first transfer means establishing transfer paths into the first cells from the circuit of said first means and establishing transfer paths out of the second cells to the circuit of the first means; and second transfer means for each row for establishing parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means establishing a path for serially transferring bits of information between all cells in a row and the circuit of the corresponding second means.

Claim 34

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means, each of said pairs of cells comprising first and second cells; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row, said first transfer means establishing transfer paths into the first cells from the circuit of said first means and establishing transfer paths out of the second cells to the circuit of the first means; and second transfer means for each row for establishing parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means establishing a path for serially transferring bits of information between all cells in a row and the circuit of the corresponding second means.

Claim 35

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means, each of said pairs of cells comprising first and second cells; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row; and second transfer means for each row for establishing parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means establishing a path for serially transferring bits of information between all cells in a row and the corresponding second means, said second transfer means establishing transfer paths into the second cells from the corresponding second means and establishing transfer paths out of the first cells to the corresponding second means.

Claim 36

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means, each of said pairs of cells comprising first and second cells; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row; and second transfer means for each row for establishing parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means establishing a path for serially transferring bits of information between all cells in a row and the corresponding second means, said second transfer means establishing transfer paths into the second cells from the corresponding second means and establishing transfer paths out of the first cells to the corresponding second means.

Claim 37

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means, each of said pairs of cells comprising first and second cells; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row, said first transfer means establishing transfer paths into the first cells from the circuit of the first means and establishing transfer paths out of the second cells to the circuit of the first means; and second transfer means for each row for establishing parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means establishing a path for serially transferring bits of information between all cells in a row and the corresponding second means, said second transfer means establishing transfer paths into the second cells from the corresponding second means and establiShing transfer paths out of the first cells to the corresponding second means.

Claim 38

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means, each of said pairs of cells comprising first and second cells; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row, said first transfer means establishing transfer paths into the first cells from the circuit of the first means and establishing transfer paths out of the second cells to the circuit of the first means; and second transfer means for each row for establishing parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means establishing a path for serially transferring bits of information between all cells in a row and the corresponding second means, said second transfer means establishing transfer paths into the second cells from the corresponding second means and establiShing transfer paths out of the first cells to the corresponding second means.

Claim 39

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row, said first transfer means comprising means for addressing any row and means for simultaneously transferring bits between the cells in the addressed row and the circuit of the first means; and second transfer means for each row for establishing parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means establishing a path for serially transferring bits of information between all cells in a row and the corresponding second means.

Claim 40

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row, said first transfer means comprising means for addressing any row and means for simultaneously transferring bits between the cells in the addressed row and the circuit of the first means; and second transfer means for each row for establishing parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means establishing a path for serially transferring bits of information between all cells in a row and the corresponding second means.

Claim 41

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row; and second transfer means for each row for establishing parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means establishing a path for serially transferring bits of information between all cells in a row and the corresponding second means, said second transfer means comprising means for simultaneously addressing a cell in each row and means for transferring bits between the addressed cells and the circuit of the second means corresponding to the row from which a bit is transferred.

Claim 42

Digital data processing system, the combination comprising: first means having a circuit for transferring a word of bit signals, parallel by bit; a plurality of second means, each having a circuit for transferring a word of bit signals, serial by bit; a matrix of pairs of bit storing cells connected in multiple rows and multiple columns, one row corresponding to each second means; first transfer means establishing a parallel bit transfer path between the circuit of said first means and all cells in any row; and second transfer means for each row for establishing parallel paths between each row of cells and the second means corresponding to each such row, said second transfer means establishing a path for serially transferring bits of information between all cells in a row and the corresponding second means, said second transfer means comprising means for simultaneously addressing a cell in each row and means for transferring bits between the addressed cells and the circuit of the second means corresponding to the row from which a bit is transferred.

Claim 43

Serial-parallel memory buffer system comprising: a. a plurality of bistable state memory cells grouped into rows and columns; b. a first gating circuit for each cell coupled to the corresponding cell; c. a second gating circuit for each cell coupled to the corresponding cell; d. a parallel input or output circuit comprising a first circuit for each of such columns for carrying, one by one, binary digital signals, each first circuit being coupled to each of the first gating circuits which are coupled to the cells in the corresponding column; e. first means for each row, the first means being coupled in common to an input of each first gating circuit which is coupled to the cells in the corresponding row, each first means being adapted for simultaneously providing a control signal to all first gating circuits in the corresponding row and the first gating circuit being responsive thereto for coupling a binary signal between the first circuit for the corresponding column and the corresponding cell; f. a serial input or output comprising a second circuit for each of such rows for carrying, one by one, binary digital signals, each of the second circuits being coupled to each of the second gating circuits which are coupled to the cells in the corresponding row; and g. second means for each row, each second means being connected in common to an input of a second gating circuit for a different cell in each row, each second means being adapted for providing a control signal in common to all connected second gating circuits and the second gating circuits being responsive thereto for coupling a binary signal between the second circuit for the corresponding row and the corresponding cell.

Claim 44

Serial-parallel memory buffer system comprising: a. a plurality of bistable state memory cells grouped into rows and columns; b. a first gating circuit for each cell coupled to the corresponding cell; c. a second gating circuit for each cell coupled to the corresponding cell; d. a parallel input or output circuit comprising a first circuit for each of such columns for carrying, one by one, binary digital signals, each first circuit being coupled to each of the first gating circuits which are coupled to the cells in the corresponding column; e. first means for each row, the first means being coupled in common to an input of each first gating circuit which is coupled to the cells in the corresponding row, each first means being adapted for simultaneously providing a control signal to all first gating circuits in the corresponding row and the first gating circuit being responsive thereto for coupling a binary signal between the first circuit for the corresponding column and the corresponding cell; f. a serial input or output comprising a second circuit for each of such rows for carrying, one by one, binary digital signals, each of the second circuits being coupled to each of the second gating circuits which are coupled to the cells in the corresponding row; and g. second means for each row, each second means being connected in common to an input of a second gating circuit for a different cell in each row, each second means being adapted for providing a control signal in common to all connected second gating circuits and the second gating circuits being responsive thereto for coupling a binary signal between the second circuit for the corresponding row and the corresponding cell.

Claim 45

The serial-parallel memory buffer system of claim 28 wherein said first means comprises an address storage means for storing a signal uniquely identifying any such row of cells whose first gating circuit is to receive a control signal.

Claim 46

The serial-parallel memory buffer system of claim 24 wherein said second means comprises an address storage means for storing a signal uniquely identifying any one group of second gating circuits having commonly connected inputs to receive a control signal.

Claim 47

The serial-parallel memory buffer system of claim 30 wherein said address storage means comprises a counter for sequentially addressing groups of second gating circuits sequentially one by one in a predetermined order.

Claim 48

The serial-parallel memory buffer system of claim 31 wherein said first means comprises an address storage means for storing a signal uniquely identifying any such row of cells whose first gating circuit is to receive a control signal.

Claim 49

The serial-parallel memory buffer system of claim 28 wherein the first gating circuit is characterized for gating a binary signal into a cell from a first circuit and the second gating circuit is characterized for gating a binary signal out of a cell to a second circuit.

Claim 50

The serial-parallel memory buffer system of claim 31 comprising: a. a further bistable state memory cell associated with each first mentioned cell; b. a third gating circuit for each further cell having an input coupled to an output of the corresponding further cell; c. a fourth gating circuit for each further cell having an output coupled to an input of the corresponding further cell; d. a parallel output circuit comprising a third circuit for each of such columns for carrying, one by one, binary digital signals, each third circuit being coupled to an output of each of the third gating circuits which are coupled to the further cells in the corresponding column; e. third means for each row, the third means being coupled in common to an input of each third gating circuit which is coupled to an input of the further cells in the corresponding row, each third means being adapted for providing a control signal to all third gating circuits in the corresponding row and the third gating circuits being responsive thereto for coupling a binary signal to the third circuits from the corresponding cells; f. a serial input comprising a fourth circuit for each of such rows for carrying, one by one, binary digital signals, each of the fourth circuits being coupled to an input of each of the fourth gating circuits which are coupled to the cells in the corresponding row; and g. fourth means for each row, each fourth means being connected in common to an input of a fourth gating circuit for a different cell in each row, each fourth means being adapted for providing a control signal in common to all connected fourth gating circuits and the second gating circuits being responsive thereto for coupling a binary signal from the second circuit for the corresponding row to the corresponding cell.