Approximator for square root of sums of squares

Claim 2

The combination comprising: source means for providing first and second input magnitude signals; comparing means responsive to said first and second input signals for producing a first signal indicating that said second input signal is greater than half of said first input signal and a second signal indicating that said first input signal is greater than half of said second input signal; summing means responsive to the source means for producing an output signal representing half the sum of said first and second input signals; and means responsive to the comparing means and to the summing means for producing an output signal representing the value of said first input signal plus one-fourth the second input signal when said first signal from said comparing means is present and said second signal from said comparing means is absent, representIng the value of said second input signal plus one-fourth the value of said second input signal when said first signal from said comparing means is absent and said second signal from said comparing means is present, and representing the value of three-fourths the sum of said first and second input signals when both said first signal and said second signal from said comparing means are present.

Claim 3

The combination comprising: source means for providing signals indicative of two values; first and second comparator means responsive to the source means for providing first and second output signals, respectively, each indicative of the relative magnitudes of one of the two values to half the other; scaler means responsive to the source means for producing quotient signals by dividing one of said values by four in response to said first comparator output signal and by dividing the other of said values by four in response to said second comparator output signal; first adder means coupled to said source means for producing output signals indicative of half the sum of the two values; second adder means responsive to said quotient signals from said scaler for producing signals indicative of the sum of said quotient signals; combining means coupled to said first and second comparator means for producing a signal of a first value when said first and second output signals from said first and second comparator both indicate one relation of said two values and for producing a signal of a second value when at least one of said first and second output signals from said first and second comparator means indicates the other relation of said two values; gating means coupled to said combining means and said first adder means for producing output signals representative of a value of zero when the output signal from said combining means has the first value and representative of the value of the output signals from said first adder means when the output signal from said combining means has the second value; and third adder means coupled to the second adder means and the gating means for producing output signals representative of the sum of the output signals from said second adder means and from said gating means.

Claim 4

The combination comprising: source means for providing signals indicative of two values; first and second comparator means responsive to the source means for providing first and second output signals, respectively, each indicative of the relative magnitudes of one of the two values to half the other; scaler means responsive to the source means for producing quotient signals by dividing one of said values by four in response to said first comparator output signal and by dividing the other of said values by four in response to said second comparator output signal; first adder means coupled to said source means for producing output signals indicative of half the sum of the two values; second adder means responsive to said quotient signals from said scaler for producing signals indicative of the sum of said quotient signals; combining means coupled to said first and second comparator means for producing a signal of a first value when said first and second output signals from said first and second comparator both indicate one relation of said two values and for producing a signal of a second value when at least one of said first and second output signals from said first and second comparator means indicates the other relation of said two values; gating means coupled to said combining means and said first adder means for producing output signals representative of a value of zero when the output signal from said combining means has the first value and representative of the value of the output signals from said first adder means when the output signal from said combining means has the second value; and third adder means coupled to the second adder means and the gating means for producing output signals representative of the sum of the output signals from said second adder means and from said gating means.

Claim 5

The invention as claimed in claim 2 wherein said first and second input magnitude signals are electrical signals representing binary numbers; and said scaler means includes a binary bit shift means for moving each bit signal of the signal to be divided to the second lower significance position.

Claim 6

The invention as claimed in claim 3 further including first retiming means for storing the first and second input signals and said first and second signals from said first and second comparator means; second retiming means for storing the output signals from said first adder means; third retiming means for storing the signals from said scaler means; fourth retiming means for storing the signals in said second retiming means; and fifth retiming means for storing the signals from said second adder means.

Claim 7

The invention as claimed in claim 4 wherein said first and second comparator means each comprise subtractor means and said first and second output signals represent borrow signals from the most significant bit positions.