Patent US3921164A successfully refreshed from Google Patents.
US3921164A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Character generator for a high resolution dot matrix display
Assignee: Unisys Corp
•
Filing: 1974-06-03
•
Granted: 1975-11-18
•
Expires: 1994-06-03
Abstract
Abstract A character generator for a dot-matrix type alpha-numeric display device whereby the resolution of the characters to be displayed is greatly increased without a corresponding increase in the size of the Read-Only Memory (ROM) utilized to store the dot patterns defining the characters to be formed. This result is accomplished by providing circuitry external to the ROM which quadruples the number of dots normally comprisiing an alphanumeric character. In addition, a smoothing circuit is provided which causes predetermined dots in the dot-matrix to be illuminated or extinguished so as to improve the overall continuity of the dot patterns defining the characters, yielding a more pleasing representation of those characters.
Inventors
- 👤 Bruce M Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:01
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/04; G06; G06K; G06K15/00; G06K15/02; G06K15/10; G09G1/00; G09G1/06; G09G1/14; G09G1/16; G09G5/00; G09G5/22; G09G5/24; G09G5/28; G06K2215/00; G06K2215/0002; G06K2215/004; G06K2215/0054; G06K2215/0057; G06K2215/006
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
287 words
In a dot-matrix type character display of the type including a read-only memory for storing at addressable locations therein a plurality of matrices of binary signals each M rows by N columns, each signal indicative of tHe lighted or unlighted condition of discrete dot groups to be displayed on a display medium in presenting a selected character from a subset of such characters, addressing means for selecting one of said plurality of matrices, and row selecting means for sequentially reading out from said read-only memory in parallel the binary signals comprising the rows of said selected one of said matrices, the improvement comprising: a. a first shift register connected to receive the parallel output signals from said read-only memory; b. a second shift register connected to receive the parallel output signals from said first shift register; c. a third shift register connected to receive the parallel output signals from said second shift register; d. a smoothing circuit comprised of digital type logic circuits connected to receive, in parallel, the outputs from predetermined stages of said first, second and third shift registers for producing a lighting control signal indicating that a discrete dot on said display medium should be lighted when the binary signals stored in said read-only memory for said selected character dictate that either the dot group including said discrete dot is to be lighted, or both of the dot groups adjacent to said one discrete dot are to be lighted and the dot group diagonally adjacent to said one discrete dot is not to be lighted; and e. output selector means connected to the output of said smoothing circuit and to said row selecting means for applying said lighting control signal to said display medium.
Claim 2
Dependent Claim
287 words
In a dot-matrix type character display of the type including a read-only memory for storing at addressable locations therein a plurality of matrices of binary signals each M rows by N columns, each signal indicative of tHe lighted or unlighted condition of discrete dot groups to be displayed on a display medium in presenting a selected character from a subset of such characters, addressing means for selecting one of said plurality of matrices, and row selecting means for sequentially reading out from said read-only memory in parallel the binary signals comprising the rows of said selected one of said matrices, the improvement comprising: a. a first shift register connected to receive the parallel output signals from said read-only memory; b. a second shift register connected to receive the parallel output signals from said first shift register; c. a third shift register connected to receive the parallel output signals from said second shift register; d. a smoothing circuit comprised of digital type logic circuits connected to receive, in parallel, the outputs from predetermined stages of said first, second and third shift registers for producing a lighting control signal indicating that a discrete dot on said display medium should be lighted when the binary signals stored in said read-only memory for said selected character dictate that either the dot group including said discrete dot is to be lighted, or both of the dot groups adjacent to said one discrete dot are to be lighted and the dot group diagonally adjacent to said one discrete dot is not to be lighted; and e. output selector means connected to the output of said smoothing circuit and to said row selecting means for applying said lighting control signal to said display medium.
Claim 3
Dependent Claim
40 words
Apparatus as in claim 1 and further including a detector circuit having its input coupled to said addressing means and its output coupled to said smoothing circuit for disabling said smoothing circuit upon the detection of a predetermined character address.
Claim 4
Dependent Claim
102 words
Apparatus as in claim 1 wherein said row selecting means includes: a. a row counter for registering a count indicative of which of the M rows of binary signals is stored in said second shift register; b. a column counter for registering a count indicative of which of the binary signals in the row indicated by said row counter is currently being displayed; c. control means for periodically incrementing said column counter and developing a shift control signal each time said column count is odd; and d. means for applying said shift control signal to said first, second and third shift registers.
Claim 5
Dependent Claim
33 words
Apparatus as in claim 3 and further including means in said control means for incrementing said row counter and clearing said column counter each time the count in said column counter reaches 2N-1.
Claim 6
Dependent Claim
87 words
Apparatus as in claim 4 and further including: a. means in said control means for producing gating control signals each time said row count is odd; and b. means for applying said gating control signals to said first, second and third shift registers for transferring, in parallel, the contents of said second register to said third register, the contents of said first register to said second register and the contents of the row of said read-only memory selected by said row selecting means to said first register.
Claim 7
Dependent Claim
25 words
Apparatus as in claim 5 and further including: a. means in said control means for terminating said incrementing means when said row count reaches 2M-1.
Claim 8
Dependent Claim
165 words
Apparatus as in claim 2 wherein said smoothing circuit comprises: a. a first rank of NOR circuits equal in number to the number of dots in said discrete dot groups; b. a first rank of NAND gates equal in number to the number of dots in said discrete dot groups, each having one input connected to the output of a different one of said NOR circuits in said first group and the remaining inputs coupled to the output from predetermined stages of said first, second and third shift registers; c. a second rank of NAND gates each having a first input individually connected to the output from a NAND gate in said first rank of NAND gaTes and a second input of each coupled to a predetermined stage of said second shift register; and d. means connecting the outputs from the NAND gates in said second rank to the inputs of said NOR circuits in said first rank in accordance with a predetermined priority schedule.
Claim 9
Dependent Claim
31 words
Apparatus as in claim 7 and further including means coupling the output of detector circuit to an input of each of said NOR circuits in said first rank of NOR circuits.
Claim 10
Dependent Claim
272 words
In a dot-matrix type character display of the type including a read-only memory for storing at addressable locations therein a plurality of matrices of binary signals, each M rows by N columns, each signal indicative of the presence or absence of a visible indicia of discrete dot groups to be imposed on an observable medium by a utilization device in presenting a selected character from a subset of said characters, addressing means for selecting one of said plurality of matrices, and row selecting means for sequentially reading out from said read-only memory in parallel the binary signals comprising the rows of said selected one of said matrices, the improvement comprising: a. a first register connected to receive the parallel output signals from said read-only memory; b. a second register connected to receive, in parallel, the outputs from said first register; c. smoothing circuit means comprised of digital type logic circuits connected to receive the outputs from predetermined stages of said first and second registers for producing one or more control signals indicating that other discrete dots on said medium should be rendered visible when the binary signals stored in said read-only memory for said selected character dictate that either the dot groups including said discrete dots are to be rendered visible or both of the dot groups adjacent to a discrete dot are to be rendered visible and the dot group diagonally adjacent to said discrete dot is not to be rendered visible; and d. output selector means connected to the output of said smoothing circuit means and to said row selecting means for connecting said control signal(s) to said utilization device.
Claim 11
Dependent Claim
272 words
In a dot-matrix type character display of the type including a read-only memory for storing at addressable locations therein a plurality of matrices of binary signals, each M rows by N columns, each signal indicative of the presence or absence of a visible indicia of discrete dot groups to be imposed on an observable medium by a utilization device in presenting a selected character from a subset of said characters, addressing means for selecting one of said plurality of matrices, and row selecting means for sequentially reading out from said read-only memory in parallel the binary signals comprising the rows of said selected one of said matrices, the improvement comprising: a. a first register connected to receive the parallel output signals from said read-only memory; b. a second register connected to receive, in parallel, the outputs from said first register; c. smoothing circuit means comprised of digital type logic circuits connected to receive the outputs from predetermined stages of said first and second registers for producing one or more control signals indicating that other discrete dots on said medium should be rendered visible when the binary signals stored in said read-only memory for said selected character dictate that either the dot groups including said discrete dots are to be rendered visible or both of the dot groups adjacent to a discrete dot are to be rendered visible and the dot group diagonally adjacent to said discrete dot is not to be rendered visible; and d. output selector means connected to the output of said smoothing circuit means and to said row selecting means for connecting said control signal(s) to said utilization device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-17 | 1979-05-19 | 1979-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-17 | 1983-05-19 | 1983-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-17 | 1987-05-19 | 1987-11-18 | $7700.00 | Window Closed / Lapsed |