Three-rank priority select register system for fail-safe priority determination

Claim 2

A fail-safe priority system, comprising: a receiving register comprised of N request receive FFs for receiving priority request signals; a three-rank holding register comprises of three priority select registers A, B and C each of which is comprised of N priority select FFs; means for coupling the output of each of said N request receive FFs as an input to the like-ordered priority select FF of said priority select registers A, B and C; means successively coupling an enabling signal to the N priority select FFs of said priority select registers A, B and C for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select registers A, B and C at successive delay periods; means coupled to the outputs of the like-ordered priority select FFs of said priority select registers A and C for generating a signal when the states of any of the like-ordered priority select FFs of said priority select registers A and C are different.

Claim 3

A fail-safe priority system, comprising: a receiving register comprised of N request receive FFs each receiving an associated one of N priority request signals; a three-rank holding register comprised of three priority select registers A, B and C each of which is comprised of N priority select FFs; means for coupling each of the outputs of each of said N request receive FFs as an input to the like-ordered priority select FFs of said priority select registers A, B and C; an enabling means for generating an enabling signal; means for coupling each of the outputs of said N request receive FFs as first inputs to said enabling means; means coupling a CNP signal to said enabling means for enabling one or more of each of the outputs of each of said N request receive FFs to generate said enabling signal; means coupling said enabling signal to each of the N priority select FFs of said priority select register A for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register A; delay means coupled to the output of said enabling means for generating first and second delayed enabling signals; means coupling said first delayed enabling signal to each of the N priority select FFs of said priority select register B for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register B; means coupling said second delayed enabling signal to each of the N priority select FFs of said priority select register C for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register C; N comparator means; means coupling the output of the like-ordered priority select FFs of said priority select registers A and C to a like-ordered one of said N comparator means for generating a memory cycle abort signal when the states of any of the like-ordered priority select FFs of said priority select registers A and C are different.

Claim 4

A fail-safe priority system, comprising: a receiving register comprised of N request receive FFs each receiving an associated one of N priority request signals; a three-rank holding register comprised of three priority select registers A, B and C each of which is comprised of N priority select FFs; means for coupling each of the outputs of each of said N request receive FFs as an input to the like-ordered priority select FFs of said priority select registers A, B and C; an enabling means for generating an enabling signal; means for coupling each of the outputs of said N request receive FFs as first inputs to said enabling means; means coupling a CNP signal to said enabling means for enabling one or more of each of the outputs of each of said N request receive FFs to generate said enabling signal; means coupling said enabling signal to each of the N priority select FFs of said priority select register A for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register A; delay means coupled to the output of said enabling means for generating first and second delayed enabling signals; means coupling said first delayed enabling signal to each of the N priority select FFs of said priority select register B for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register B; means coupling said second delayed enabling signal to each of the N priority select FFs of said priority select register C for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register C; N comparator means; means coupling the output of the like-ordered priority select FFs of said priority select registers A and C to a like-ordered one of said N comparator means for generating a memory cycle abort signal when the states of any of the like-ordered priority select FFs of said priority select registers A and C are different.

Claim 5

The fail-safe priority system of claim 2 in which said delay means generates said first and second delayed enabling signals of respective delay periods for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select registers B and C at successively greater delay periods after said enabling signal has gated said priority request signals into the like-ordered priority Select FFs of said priority select register A.

Claim 6

A fail-safe priority system, comprising: a receiving register comprised of N request receive FFs each receiving a dedicated one of N priority request signals; a three-rank holding register comprised of the three priority select registers A, B and C, each of which is comprised of N priority select FFs; means for coupling each of the outputs of each of said N request receive FFs as inputs to the like-ordered priority select FFs of said priority select registers A, B and C; an enabling means for generating an enabling signal; means for coupling each of the outputs of said N request receive FFs as first inputs to said enabling means; means coupling a CNP signal to said enabling means for enabling one or more of each of the outputs of each of said N request receive FFs to generate said enabling signal; means coupling said enabling signal to each of the N priority select FFs of said priority select register A for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register A; delay means coupled to the output of said enabling means for generating first and second delayed enabling signals; means coupling said first delayed enabling signal to each of the N priority select FFs of said priority select register B for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register B; means coupling said second delayed enabling signal to each of the N priority select FFs of said priority select register C for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register C; N Exclusive OR means; means coupling the outputs of the like-ordered priority select FFs of said priority select registers A and C to a like-ordered one of said N Exclusive OR means for generating a memory cycle abort signal when the states of any of the like-ordered priority select FFs of said priority select registers A and C are different; a 1-out-of-N priority network; an associated memory unit; means coupling the outputs of the priority select FFs of said priority select register B to said 1-out-of-N priority network for enabling said associated memory unit to honor the highest priority one of said priority request signals unless aborted by said memory cycle abort signal.

Claim 7

A fail-safe priority system, comprising: a receiving register comprised of N request receive FFs each receiving a dedicated one of N priority request signals; a three-rank holding register comprised of the three priority select registers A, B and C, each of which is comprised of N priority select FFs; means for coupling each of the outputs of each of said N request receive FFs as inputs to the like-ordered priority select FFs of said priority select registers A, B and C; an enabling means for generating an enabling signal; means for coupling each of the outputs of said N request receive FFs as first inputs to said enabling means; means coupling a CNP signal to said enabling means for enabling one or more of each of the outputs of each of said N request receive FFs to generate said enabling signal; means coupling said enabling signal to each of the N priority select FFs of said priority select register A for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register A; delay means coupled to the output of said enabling means for generating first and second delayed enabling signals; means coupling said first delayed enabling signal to each of the N priority select FFs of said priority select register B for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register B; means coupling said second delayed enabling signal to each of the N priority select FFs of said priority select register C for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select register C; N Exclusive OR means; means coupling the outputs of the like-ordered priority select FFs of said priority select registers A and C to a like-ordered one of said N Exclusive OR means for generating a memory cycle abort signal when the states of any of the like-ordered priority select FFs of said priority select registers A and C are different; a 1-out-of-N priority network; an associated memory unit; means coupling the outputs of the priority select FFs of said priority select register B to said 1-out-of-N priority network for enabling said associated memory unit to honor the highest priority one of said priority request signals unless aborted by said memory cycle abort signal.

Claim 8

The fail-safe priority system of claim 4 in which said delay means generates said first and second delayed enabling signals of respective delay periods for gating the priority request signals received by the request receive FFs of said receiving register into the like-ordered priority select FFs of said priority select registers B and C at successively greater delay periods with respect to said enabling signal.