Abstract Computer handling a binary representation of an index for an entry in a computer table to determine if the index is an odd or even multiple of the number of addressable units (i.e. bytes, characters, or words) in the length of an entry in the table. A mask field is generated and used in making the odd or even determination by identifying the bit position of the lower-order one bit value in the binary representation of the entry length. If the index is determined to be an odd multiple, an adjustment is made to the number of addressable units in the index prior to its use in generating a next index, so that the adjusted index is an even multiple. No adjustment is provided to the current index if it is determined to be an even multiple. When used within a binary search, the address generated to represent the next index will be boundary aligned to the beginning of a table entry. The next index is generated by a right shift (i.e. a shift of one bit position toward its lowest order bit) of the adjusted binary number representation of the current index. The even multiple adjustment assures that no remainder can be generated by a shift operation, which provides a remainderless binary divide-by-two.
Inventors
👤 Luther J Woodrum
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-08 15:07
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/04
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
121 words
A system for controlling an index register which contains contents in addressable units for accessing a table, comprising index register means for containing a binary field representing the number of addressable units in an entry length in said table, means for providing a mask field identifying the position of the lowest-order 1 bit in said index register, means for signalling a 0 or 1 value of a bit in the index register at a bit position identified by said mask field, and means for adjusting the content of said index register if said bit position tested by said signalling means finds a 1 value, whereby the content of said index register is adjusted for the generation of a next index value.
Claim 2
Independent Claim
121 words
A system for controlling an index register which contains contents in addressable units for accessing a table, comprising index register means for containing a binary field representing the number of addressable units in an entry length in said table, means for providing a mask field identifying the position of the lowest-order 1 bit in said index register, means for signalling a 0 or 1 value of a bit in the index register at a bit position identified by said mask field, and means for adjusting the content of said index register if said bit position tested by said signalling means finds a 1 value, whereby the content of said index register is adjusted for the generation of a next index value.
Claim 3
Dependent Claim
77 words
A system as defined in claim 1, further comprising said adjusting means including means for subtracting said binary field from the content of said index register if said signalling means finds a 1 value, and means for shifting the content of the index register by one bit position in the direction of its lowest-order bit position, whereby the content of said index register after said shifting means contains a next index to be accessed in said table.