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US3921142A Expired / Lapsed US ⏱️ 0.0 years remaining

Electronic calculator chip having test input and output

Assignee: Texas Instruments Inc
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Filing: 1973-09-24
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Granted: 1975-11-18
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Expires: 1993-09-24
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Abstract

Abstract An MOS/LSI semiconductor chip for providing the functions of an electronic calculator includes a data memory, an arithmetic unit for executing operations on data from the memory, and a control arrangement for defining the functioning of the machine including a ROM for storing a large number of instruction words, an instruction register for receiving instruction words from the ROM and reading out parts to various sections of the control arrangement, and an address register for selecting the location in the ROM for read out of the next instruction. Input and output terminals are provided for keyboard input, display output, timing signals, etc. A test mode of operation is provided for quality control upon completion of manufacture of the chip. The test mode allows the entire ROM to be tested by reading in addresses to the address register from external and reading out the resulting word from the instruction register. During the test mode, normal incrementing and branching of the address register may be externally inhibited.

Inventors

  • 👤 John D Bryant
  • 👤 Glenn A Hartsell

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 21:23
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/126; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31721; G06; G06F; G06F15/00; G06F15/02

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 147 words
A SEMICONDUCTOR CHIP FOR PROVIDING THE FUNCTIONS OF A CALCULATOR, COMPRISING A READ-ONLY-MEMORY FOR STORING A LARGE NUMBER OF INSTRUCTION WORDS, CIRCUIT MEANS CONNECTED TO RECEIVE INSTRUCTION WORDS FROM THE READ-ONLY-MEMORY AND HAVING OUTPUTS, CONTROL MEANS FOR DEFINING THE OPERATION OF THE CALCULATOR, THE CONTROL MEANS HAVING INPUTS CONNECTED TO OUTPUTS OF THE CIRCUIT MEANS, ADDRESS REGISTER MEANS FOR DEFINING A LOCATION IN THE READ-ONLY-MEMORY, CHARACTERIZED IN THAT A TEST MODE OF OPERATION OF THE CALCULATOR IS PROVIDED WHEREIN OPERATION IS DIFFERENT FROM OPERATION IN THE CALCULATE MODE, MEANS CONNECTING ONE OF THE TERMINALS OF THE SEMICONDUCTOR CHIP TO THE ADDRESS REGISTER MEANS TO PERMIT READING IN TO THE ADDRESS REGISTER MEANS A SPECIFIC ADDRESS FROM AN EXTERNAL SOURCE, AND MEANS CONNECTING ANOTHER OF THE TERMINALS OF THE SEMICONDUCTOR CHIP TO SAID CIRCUIT MEANS FOR READING OUT TO EXTERNAL UTILIZATION MEANS AN INSTRUCTION WORD FROM THE READ-ONLY-MEMORY.
Claim 2
Dependent Claim 147 words
A SEMICONDUCTOR CHIP FOR PROVIDING THE FUNCTIONS OF A CALCULATOR, COMPRISING A READ-ONLY-MEMORY FOR STORING A LARGE NUMBER OF INSTRUCTION WORDS, CIRCUIT MEANS CONNECTED TO RECEIVE INSTRUCTION WORDS FROM THE READ-ONLY-MEMORY AND HAVING OUTPUTS, CONTROL MEANS FOR DEFINING THE OPERATION OF THE CALCULATOR, THE CONTROL MEANS HAVING INPUTS CONNECTED TO OUTPUTS OF THE CIRCUIT MEANS, ADDRESS REGISTER MEANS FOR DEFINING A LOCATION IN THE READ-ONLY-MEMORY, CHARACTERIZED IN THAT A TEST MODE OF OPERATION OF THE CALCULATOR IS PROVIDED WHEREIN OPERATION IS DIFFERENT FROM OPERATION IN THE CALCULATE MODE, MEANS CONNECTING ONE OF THE TERMINALS OF THE SEMICONDUCTOR CHIP TO THE ADDRESS REGISTER MEANS TO PERMIT READING IN TO THE ADDRESS REGISTER MEANS A SPECIFIC ADDRESS FROM AN EXTERNAL SOURCE, AND MEANS CONNECTING ANOTHER OF THE TERMINALS OF THE SEMICONDUCTOR CHIP TO SAID CIRCUIT MEANS FOR READING OUT TO EXTERNAL UTILIZATION MEANS AN INSTRUCTION WORD FROM THE READ-ONLY-MEMORY.
Claim 3
Dependent Claim 41 words
A semiconductor chip according to claim 1 wherein a control input is connected to means within the chip for controlling branching to a nonadjacent address in the read-only-memory by loading an address into the address register means from the circuit means.--
Claim 4
Dependent Claim 83 words
In data processing apparatus, a ROM, address register means for defining a location in the ROM, circuit means for receiving instruction words from the ROM, means for incrementing the address register and for branching to a remote location in the ROM using an address defined by the circuit means, and means for reading addresses into the address register from an external source and reading instruction words out to external utilization means via the circuit means while inhibiting said means foR incrementing and branching.--
Claim 5
Dependent Claim 83 words
In data processing apparatus, a ROM, address register means for defining a location in the ROM, circuit means for receiving instruction words from the ROM, means for incrementing the address register and for branching to a remote location in the ROM using an address defined by the circuit means, and means for reading addresses into the address register from an external source and reading instruction words out to external utilization means via the circuit means while inhibiting said means foR incrementing and branching.--
Claim 6
Dependent Claim 32 words
In data processing appaaratus according to claim 3, data inputs to the apparatus, and means for inhibiting said incrementing and branching by control signals coupled into the apparatus via said data inputs.
Claim 7
Dependent Claim 24 words
In data processing apparatus according to claim 3, the apparatus comprising a semiconductor integrated circuit containing the ROM, address register means and circuit means.
Claim 8
Dependent Claim 31 words
In data processing apparatus according to claim 3, a test control input for disenabling normal operation and enabling a test mode of operation when reading addresses into the address register means.
Claim 9
Dependent Claim 166 words
A semiconductor chip for providing the functions of a calculator, comprising a data memory for storing numerical data, arithmetic means having inputs and outputs selectively connected to the data memory, a read-only-memory for storing a large number of instruction words, address register means for defining a location in the read-only-memory, circuit means connected to receive instruction words from the read-only-memory and having outputs connected to control means for defining the operation of the calculator, a plurality of input/output means for entering numerical data and functional commands into the semiconductor chip as from a keyboard and outputing data as to a display characterized in that means are provided for operation of the semiconductor chip in a test mode of operation, such means including conductor means connecting first of the input/output means to the address register means to permit reading in an address from an external source, and further including conductor means connecting second of the input/output means via the circuit means for reading out an instruction word.
Claim 10
Dependent Claim 166 words
A semiconductor chip for providing the functions of a calculator, comprising a data memory for storing numerical data, arithmetic means having inputs and outputs selectively connected to the data memory, a read-only-memory for storing a large number of instruction words, address register means for defining a location in the read-only-memory, circuit means connected to receive instruction words from the read-only-memory and having outputs connected to control means for defining the operation of the calculator, a plurality of input/output means for entering numerical data and functional commands into the semiconductor chip as from a keyboard and outputing data as to a display characterized in that means are provided for operation of the semiconductor chip in a test mode of operation, such means including conductor means connecting first of the input/output means to the address register means to permit reading in an address from an external source, and further including conductor means connecting second of the input/output means via the circuit means for reading out an instruction word.

References Cited (Backward Citations)

US3427443A Cited
US3575589A Cited
US3602894A Cited
US3593313A Cited
US3693162A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-11-17 1979-05-19 1979-11-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-11-17 1983-05-19 1983-11-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-11-17 1987-05-19 1987-11-18 $7700.00 Window Closed / Lapsed

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