Patent US3921139A successfully refreshed from Google Patents.
US3921139A
Expired / Lapsed
US
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Test system having memory means at test module
Assignee: Westinghouse Electric Corp
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Filing: 1974-03-08
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Granted: 1975-11-18
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Expires: 1994-03-08
Abstract
Abstract A system for independently determining the operational status of one or more circuits or units is disclosed. The system includes one or more test modules with at least one module being associated with each unit or circuit to be tested. The test modules communicate with a test console via address and results data busses. The individual modules may continually test the associated unit and communicate the results of the test to the console on request or the test may be initiated by signals generated by the console and the results of the test communicated to the console on request. The console may be manually operated, that is, the operator specifies what test is to be performed. The test may also be automatically performed under the control of programmed digital computer. Each of the test modules may be incorporated into the apparatus to be tested as the apparatus is being constructed.
Inventors
- 👤 Jr Samuel J Hardesty
- 👤 Raymond A Lloyd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2221; G06F11/26; G06F11/273; G06F11/2733
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
184 words
A test module for use as a subsection of a complex test system, said module comprising: a. test means for testing the apparatus associated with said module by comparing a digital signal indicative of the operational status of said apparatus to a digital signal stored in a memory which is part of said test module; b. gating means for gating the results of tests performed on said apparatus by said test means to a results bus; c. decoding means for receiving first and second identification signals from a test console via an address bus, said decoding means including apparatus for decoding said first identification signal to generate a signal which initiates said test means such that said test means performs predetermined tests on said associated apparatus and for decoding said second identification signal to generate a second signal which gates the results of said test to said console via said results bus; wherein d. said first and second identification signals are coded such that a plurality of said modules can communicate with a single test console by time sharing said results and address buses.
Claim 2
Dependent Claim
184 words
A test module for use as a subsection of a complex test system, said module comprising: a. test means for testing the apparatus associated with said module by comparing a digital signal indicative of the operational status of said apparatus to a digital signal stored in a memory which is part of said test module; b. gating means for gating the results of tests performed on said apparatus by said test means to a results bus; c. decoding means for receiving first and second identification signals from a test console via an address bus, said decoding means including apparatus for decoding said first identification signal to generate a signal which initiates said test means such that said test means performs predetermined tests on said associated apparatus and for decoding said second identification signal to generate a second signal which gates the results of said test to said console via said results bus; wherein d. said first and second identification signals are coded such that a plurality of said modules can communicate with a single test console by time sharing said results and address buses.
Claim 3
Dependent Claim
156 words
A test module for use as a subsection of a complex test system, said module comprising: a. test means for testing apparatus associated with said module by comparing a digital signal indicative of the operational status of said apparatus to a digital signal stored in a memory which is part of said test module; b. gating means for gating the results of test performed on said apparatus by said test means via a results bus; c. decoding means for receiving an identification signal from a test console via a first bus and a clock signal via a clock bus, said decoding means including apparatus for decoding said identification signal to generate a signal which gates the results of said test to said console via said data bus; wherein d. said identification signal is coded such that a plurality of said modules can communicate with a single console by time sharing said data and clock data buses.
Claim 4
Dependent Claim
156 words
A test module for use as a subsection of a complex test system, said module comprising: a. test means for testing apparatus associated with said module by comparing a digital signal indicative of the operational status of said apparatus to a digital signal stored in a memory which is part of said test module; b. gating means for gating the results of test performed on said apparatus by said test means via a results bus; c. decoding means for receiving an identification signal from a test console via a first bus and a clock signal via a clock bus, said decoding means including apparatus for decoding said identification signal to generate a signal which gates the results of said test to said console via said data bus; wherein d. said identification signal is coded such that a plurality of said modules can communicate with a single console by time sharing said data and clock data buses.
Claim 5
Dependent Claim
201 words
A test module for use as a subsection of a complex test system, said module comprising: a. decoding means for receiving and decoding an identification signal, said identificatiton signal being received via an address bus, said identification signal including first and second coded portions, said first portion being decoded by said decoding means to generate a test initiate signal and said second portion being decoded to generate a gate result signal; b. test means responsive to said test initiate signal for testing the apparatus associated with said module to determine its operational status, and means for gating the results of the test performed on said associated apparatus to a results bus in response to said gate signal with the operational status of said associated apparatus being determined by comparing digital signals indicative of the operational status of said apparatus to a digital signal stored in a memory which is a part of said test module; d. means permitting a plurality of said test modules to communicate with a common test console via two serial buses on a time-shared basis, with a bipolar signal being utilized to transmit said identification signals and a clock signal to said module via said address bus.
Claim 6
Dependent Claim
201 words
A test module for use as a subsection of a complex test system, said module comprising: a. decoding means for receiving and decoding an identification signal, said identificatiton signal being received via an address bus, said identification signal including first and second coded portions, said first portion being decoded by said decoding means to generate a test initiate signal and said second portion being decoded to generate a gate result signal; b. test means responsive to said test initiate signal for testing the apparatus associated with said module to determine its operational status, and means for gating the results of the test performed on said associated apparatus to a results bus in response to said gate signal with the operational status of said associated apparatus being determined by comparing digital signals indicative of the operational status of said apparatus to a digital signal stored in a memory which is a part of said test module; d. means permitting a plurality of said test modules to communicate with a common test console via two serial buses on a time-shared basis, with a bipolar signal being utilized to transmit said identification signals and a clock signal to said module via said address bus.
References Cited (Backward Citations)
US3383658A
Cited
US3435416A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-17 | 1979-05-19 | 1979-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-17 | 1983-05-19 | 1983-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-17 | 1987-05-19 | 1987-11-18 | $7700.00 | Window Closed / Lapsed |