Abstract A processor for performing a discrete cosine transform of an input signal, suitable for real-time television image processing, specifically for obtaining an acceptable picture when the number of bits of information available for describing the picture and/or the channel bandwidth are severely limited, comprising: two complex read-only memories, an input and output read-only memory, each containing a predetermined number of data points arranged in a predetermined manner; two complex multipliers, an input and an output multiplier, each having an input from one of the read-only memories, an input which is connectable to the external signal of N data values which is to be transformed discretely and cosinusoidally; a complex transversal filter, having 2N-1 taps, the input to the filter being the output of the input multiplier; the output of the transform processor comprising the output of the output multiplier.
A signal processor for performing the discrete cosine transform of an input signal having N samples, comprising: two complex read-only memories, an input and output read-only memory, each containing a total number N of data points arranged in a predetermined manner; two complex multipliers, an input and an output multiplier, each having an input from one of the read-only memories, the input multiplier having an input which is connectable to the external signal which is to be transformed discretely and cosinusoidally; and a complex transversal filter, having 2N-1 taps, the input to the filter being the output of the input multiplier; the output of the transform processor comprising the real part of the output of the output multiplier.
Claim 2
Dependent Claim
118 words
A signal processor for performing the discrete cosine transform of an input signal having N samples, comprising: two complex read-only memories, an input and output read-only memory, each containing a total number N of data points arranged in a predetermined manner; two complex multipliers, an input and an output multiplier, each having an input from one of the read-only memories, the input multiplier having an input which is connectable to the external signal which is to be transformed discretely and cosinusoidally; and a complex transversal filter, having 2N-1 taps, the input to the filter being the output of the input multiplier; the output of the transform processor comprising the real part of the output of the output multiplier.
Claim 3
Dependent Claim
29 words
The processor, according to claim 1, further comprising: means connected to the read-only memories, multipliers and filter for controlling the timing or sequencing of these three types of circuits.
Claim 4
Dependent Claim
34 words
The processor for performing a discrete cosine transform of an input signal according to claim 1, wherein: the input read-only memory has stored within it data samples corresponding to 0.5 for n 0 and
Claim 5
Dependent Claim
34 words
The processor for performing a discrete cosine transform of an input signal according to claim 1, wherein: the input read-only memory has stored within it data samples corresponding to 0.5 for n 0 and