Patent US3919699A successfully refreshed from Google Patents.
US3919699A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory circuit
Assignee: Sony Corp
•
Filing: 1974-06-28
•
Granted: 1975-11-11
•
Expires: 1994-06-28
Abstract
Abstract A memory circuit is disclosed in which a first capacitor is connected in parallel between the gate and common electrodes of an insulated gate field effect transistor, the gate electrode thereof is connected through a first switching element to one end of a second capacitor, the other end of the second capacitor is connected to the common electrode of the insulated gate field effect transistor, a second switching element is connected in series between the connection point of the first switching element and the second capacitor and an input terminal, and an output terminal is led out from the output electrode of the insulated gate field effect transistor, and in which the first and second switching elements are controlled to be ON and OFF in ganged relation.
Inventors
- 👤 Yasuhiro Hideshima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:08
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
188 words
A memory circuit, comprising: an input terminal for receiving an input voltage to be stored; an insulated gate field effect transistor having a gate electrode to which a stored voltage is applied, an output electrode for producing an output voltage proportional to said stored voltage, and a common electrode; a first capacitor having high leakage resistance connected between said gate electrode and said common electrode for storing said input voltage and for applying same to said gate electrode; a second capacitor for receiving said input voltage and having one terminal connected to said common electrode and a second terminal; first switch meAns for connecting said second terminal of said second capacitor to said gate electrode so that said first and second capacitors are connected in parallel; and second switch means ganged for simultaneous operation with said first switch means for connecting said first and second capacitors to said input terminal to enable said input voltage to be applied thereto, whereby when said first and second switch means are opened, only said first capacitor is connected to said insulated gate field effect transistor to supply said stored voltage thereto.
Claim 2
Dependent Claim
188 words
A memory circuit, comprising: an input terminal for receiving an input voltage to be stored; an insulated gate field effect transistor having a gate electrode to which a stored voltage is applied, an output electrode for producing an output voltage proportional to said stored voltage, and a common electrode; a first capacitor having high leakage resistance connected between said gate electrode and said common electrode for storing said input voltage and for applying same to said gate electrode; a second capacitor for receiving said input voltage and having one terminal connected to said common electrode and a second terminal; first switch meAns for connecting said second terminal of said second capacitor to said gate electrode so that said first and second capacitors are connected in parallel; and second switch means ganged for simultaneous operation with said first switch means for connecting said first and second capacitors to said input terminal to enable said input voltage to be applied thereto, whereby when said first and second switch means are opened, only said first capacitor is connected to said insulated gate field effect transistor to supply said stored voltage thereto.
Claim 3
Dependent Claim
22 words
A memory circuit claimed in claim 1, wherein the capacitance of the first capacitor is smaller than that of the second capacitor.
Claim 4
Dependent Claim
18 words
A memory circuit claimed in claim 1, wherein said insulated gate field effect transistor is a MOS FET.
References Cited (Backward Citations)
US3646525A
Cited
US3652914A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-10 | 1979-05-12 | 1979-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-10 | 1983-05-12 | 1983-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-10 | 1987-05-12 | 1987-11-11 | $7700.00 | Window Closed / Lapsed |