Data transmission utilizing modulation of alternate carrier cycles

Claim 2

Data transmission system utilizing modulation of alternate carrier wave cycles comprising: means for modulating said carrier wave so that said carrier wave is defined into a plurality of blocks and all the cycles but one at least within each of said blocks are subjected to amplitude modulation by a data signal; means for recording or transmitting said modulated wave; means for demodulating said modulated wave comprising means for comparing the amplitude of said unmodulated cycle of said recorded or transmitted wave with the amplitude of said modulated cycle in the same block and means for reproducing said data from the output of said comparing means; said modulating means comprising means for generating a first square wave having a width equivalent to multiples of one cycle of said carrier wave; means for feeding a head formation signal; means for storing said data signal for modulating said carrier wave in a first data memory; a ring counter supplied with said head formation signal and said first square wave to produce sequentially a plurality of second square waves defining said blocks; and gating means supplied with said head formation signal, said data signal stored in said first data memory, said first square wave and said second square wave to modulate said carrier wave by said head formation signal and said data signal.

Claim 3

Data transmission system according to claim 1 wherein said demodulating means comprises: a zero cross detector for generating a zero cross signal by detecting the zero cross position of said modulated wave; a clock pulse generator for producing a clock pulse in synchronism with said zero cross signal; a shift register having a plurality of stages which is supplied with the output from said comparing means and shifts its contents by the clock pulse from said clock pulse generator; and gating means connected to each stage of said shift register to reproduce said data signal.

Claim 4

Data transmission system according to claim 2 wherein said demodulating means further includes: a second data memory for storing said reproduced data signal; an AND gate which is supplied with said head signal from the specified stages of said shift register; and a set pulse generator which is supplied with said clock pulse and the output of said AND gate and emits a set pulse to said second data memory for delivering in parallel said data stored therein.

Claim 5

Data transmission system according to claim 1 wherein said demodulating means comprising: a zero cross detector for producing a zero cross signal by detecting the zero cross position of said modulated wave; a clock pulse generator which is supplied with the zero cross signal and generates first and second clock pulses different in phases from each other; a first reference signal formation circuit for forming a first reference signal having a level corresponding to the positive amplitude of said unmodulated cycle of said modulated wave; a second reference signal formation circuit for forming a second reference signal having a level corresponding to the negative amplitude of said unmodulated cycle of said modulated wave; a first comparator for comparing the positive amplitude of said modulated cycle with said first reference signal level to produce a first data signal included in said modulated wave; a second comparator for comparing the negative amplitude of said modulated cycle with said second signal level to produce a second data signal included in said modulated wave; an AND circuit for generating one pulse output each time the presence of a pair of corresponding pulses is detected from trains of pulses including said first and second data signals; and a data extraction circuit which is supplied with said output pulse from said AND circuit and with said first clock pulse to extract said data signal from the output of said AND circuit.

Claim 6

Data transmission system according to claim 1 wherein said demodulating means comprises a circuit for obtaining a reference signal at a level corresponding to the amplitude of said unmodulated cycle in each of said blocks of said modulated wave, said circuit comprising: a field effect transistor with said modulated wave fed to the source electrode thereof and with a capacitor connected in series to the drain electrode thereof; a switching circuit turned ON at a prescribed position close to the maximum amplitude of said unmodulated cycle within a block of said modulated wave to supply a gate-on signal to said field effect transistor for charging the capacitor with the substantial maximum amplitude; and a circuit for forming said reference signal from the interterminal voltage of said capacitor.