Patent US3919637A successfully refreshed from Google Patents.
US3919637A
Expired / Lapsed
US
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Logic circuit fault detector
Assignee: AT&T Inc
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Filing: 1974-05-22
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Granted: 1975-11-11
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Expires: 1994-05-22
Abstract
Abstract One known technique for testing a digital logic circuit assembly counts the logic level transitions at output and/or test point terminals while exercising the assembly with a fixed set of Gray code related input voltages. Many faulty assemblies are detected by the production of unexpected counts. The present disclosure teaches the addition of ONEs counting to improve the rate at which faulty assemblies are detected.
Inventors
- 👤 Ronald Lee Earp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:21
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
111 words
In test apparatus which produces a sequence of Gray code binary number related sets of outputs for application to the input terminals of a binary circuit assembly to be tested and, furthermore, which detects transitions between first and second levels on the output terminals of said assembly and indicates the number of said transitions occurring during said sequence, the improvement comprising the addition of means for detecting each time said first level occurs on at least one of said output terminals in response to each of said sets of outputs for indicating the number of said first levels occurring during said sequence, which numbers may be compared to known reference numbers.
Claim 2
Dependent Claim
111 words
In test apparatus which produces a sequence of Gray code binary number related sets of outputs for application to the input terminals of a binary circuit assembly to be tested and, furthermore, which detects transitions between first and second levels on the output terminals of said assembly and indicates the number of said transitions occurring during said sequence, the improvement comprising the addition of means for detecting each time said first level occurs on at least one of said output terminals in response to each of said sets of outputs for indicating the number of said first levels occurring during said sequence, which numbers may be compared to known reference numbers.
Claim 3
Dependent Claim
152 words
Test apparatus for testing logic circuit assemblies, said apparatus comprising, a generator for applying a sequence of Gray code related sets of inputs to one of said assemblies, a transition detector for receiving the outputs from said assembly receiving said sets of inputs to produce an output each time said assembly outputs change between first and second logic levels, a logic level detector for receiving the outputs from said assembly receiving said sets of inputs to produce, when enabled, an output each time its inputs are at said first logic level, means enabling said logic level detector in synchronism with said sets of inputs, and means connected to said transition detector and said logic level detector to indicate the number of transition detector outputs and the number of logic level detector outputs occurring during said sequence of Gray code related sets of inputs, which numbers may be compared to known reference numbers.
Claim 4
Dependent Claim
152 words
Test apparatus for testing logic circuit assemblies, said apparatus comprising, a generator for applying a sequence of Gray code related sets of inputs to one of said assemblies, a transition detector for receiving the outputs from said assembly receiving said sets of inputs to produce an output each time said assembly outputs change between first and second logic levels, a logic level detector for receiving the outputs from said assembly receiving said sets of inputs to produce, when enabled, an output each time its inputs are at said first logic level, means enabling said logic level detector in synchronism with said sets of inputs, and means connected to said transition detector and said logic level detector to indicate the number of transition detector outputs and the number of logic level detector outputs occurring during said sequence of Gray code related sets of inputs, which numbers may be compared to known reference numbers.
Claim 5
Dependent Claim
177 words
Test apparatus for testing logic circuit assemblies, said apparatus comprising, a generator which produces a sequence of Gray code binary number related sets of outputs, means for applying said sets of outputs to the input terminals of one of said assemblies, a transition detector which produces outputs each time its inputs change between first and second logic levels, means for connecting said transition detector to the output terminals of said assemBly to which said sets of outputs are applied, a logic level detector which, when enabled, produces outputs each time its inputs are at said first logic level, means enabling said logic level detector in synchronism with said sets of outputs, means for connecting said logic level detector to the output terminals of said assembly to which said sets of outputs are applied, and means connected to said transition detector and said logic level detector to indicate the number of transition detector outputs and the number of logic level detector outputs occurring during said sequence of generator outputs, which numbers may be compared to known reference numbers.
Claim 6
Dependent Claim
177 words
Test apparatus for testing logic circuit assemblies, said apparatus comprising, a generator which produces a sequence of Gray code binary number related sets of outputs, means for applying said sets of outputs to the input terminals of one of said assemblies, a transition detector which produces outputs each time its inputs change between first and second logic levels, means for connecting said transition detector to the output terminals of said assemBly to which said sets of outputs are applied, a logic level detector which, when enabled, produces outputs each time its inputs are at said first logic level, means enabling said logic level detector in synchronism with said sets of outputs, means for connecting said logic level detector to the output terminals of said assembly to which said sets of outputs are applied, and means connected to said transition detector and said logic level detector to indicate the number of transition detector outputs and the number of logic level detector outputs occurring during said sequence of generator outputs, which numbers may be compared to known reference numbers.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-10 | 1979-05-12 | 1979-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-10 | 1983-05-12 | 1983-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-10 | 1987-05-12 | 1987-11-11 | $7700.00 | Window Closed / Lapsed |