US3918148A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit chip carrier and method for forming the same
Assignee: International Business Machines Corp
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Filing: 1974-04-15
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Granted: 1975-11-11
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Expires: 1994-04-15
Abstract
Abstract An integrated circuit chip carrier with multi-level metallurgy, in which the effects of the metallurgy in causing elevation irregularitiies at the various levels of the structure are minimized, is produced by a method wherein a first plurality of levels of metallization patterns respectively separated by layers of dielectric material are first formed on a planar primary layer supported on a temporary substrate having a chemical etchability different from that of the layer. The primary layer is electrically insulative with respect to said metallization patterns. Then, a supporting layer is formed on the uppermost covering layer, after which the substrate is removed with a chemical etchant which preferentially etches the substrate away from the insulative layer. Next, an opposite plurality of levels of metallization patterns are formed on the side of the insulative layer opposite to the first formed metallization patterns. These opposite metallization patterns are also respectively separated by covering layers of dielectric material.
Inventors
- 👤 Ingrid E Magdo
- 👤 Steven Magdo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:57
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/01; H10W70/05; H10W70/611; H10W70/67; H10W70/69; H10W70/698; H10W90/00; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
155 words
A method for forming an integrated circuit chip carrier comprising forming on a substrate, a primary layer which has a chemical etcHability different from that of said substrate and is electrically insulative with respect to subsequently applied metallization patterns, forming a first level metallization pattern on the exposed surface of said primary layer, forming over said metallization pattern and said surface, a first covering layer of dielectric material, forming on said first covering layer, at least one additional level metallization pattern, forming over each additional level metallization pattern, an additional covering layer of dielectric material, forming a supporting base on the last formed additional covering layer, removing said substrate with a chemical etchant which preferentially etches said substrate to expose the other surface of said primary layer, forming at said other surface, an opposite level metallization pattern, and forming over said opposite metallization pattern and said other surface, an opposite covering layer of dielectric material.
Claim 2
Independent Claim
155 words
A method for forming an integrated circuit chip carrier comprising forming on a substrate, a primary layer which has a chemical etcHability different from that of said substrate and is electrically insulative with respect to subsequently applied metallization patterns, forming a first level metallization pattern on the exposed surface of said primary layer, forming over said metallization pattern and said surface, a first covering layer of dielectric material, forming on said first covering layer, at least one additional level metallization pattern, forming over each additional level metallization pattern, an additional covering layer of dielectric material, forming a supporting base on the last formed additional covering layer, removing said substrate with a chemical etchant which preferentially etches said substrate to expose the other surface of said primary layer, forming at said other surface, an opposite level metallization pattern, and forming over said opposite metallization pattern and said other surface, an opposite covering layer of dielectric material.
Claim 3
Independent Claim
166 words
A method for forming an integrated circuit chip carrier comprising forming on a substrate, a primary layer which is temperature stable at temperatures above 500*C, has a chemical etchability different from that of said substrate and is electrically insulative with respect to subsequently applied metallization patterns, forming a first level metallization pattern on the exposed surface of said primary layer, forming over said metallization pattern and said surface, a first covering layer of dielectric material, forming on said first covering layer, at least one additional level metallization pattern, forming over each additional level metallization pattern, an additional covering layer of dielectric material, depositing on the last formed additional covering layer, a supporting layer of polycrystalline semiconductor material, removing said substrate with a chemical etchant which preferentially etches said substrate to expose the other surface of said primary layer, forming at said other surface, an opposite level metallization pattern, and forming over said opposite metallization pattern and said other surface, an opposite covering layer of dielectric material.
Claim 4
Independent Claim
166 words
A method for forming an integrated circuit chip carrier comprising forming on a substrate, a primary layer which is temperature stable at temperatures above 500*C, has a chemical etchability different from that of said substrate and is electrically insulative with respect to subsequently applied metallization patterns, forming a first level metallization pattern on the exposed surface of said primary layer, forming over said metallization pattern and said surface, a first covering layer of dielectric material, forming on said first covering layer, at least one additional level metallization pattern, forming over each additional level metallization pattern, an additional covering layer of dielectric material, depositing on the last formed additional covering layer, a supporting layer of polycrystalline semiconductor material, removing said substrate with a chemical etchant which preferentially etches said substrate to expose the other surface of said primary layer, forming at said other surface, an opposite level metallization pattern, and forming over said opposite metallization pattern and said other surface, an opposite covering layer of dielectric material.
Claim 5
Dependent Claim
15 words
The method of claim 2 wherein said primary layer is a layer of dielectric material.
Claim 6
Dependent Claim
32 words
The method of claim 2 wherein said primary layer is a composite of a planar metallic layer interfacing with the substrate and a planar layer of dielectric material at the exposed surface.
Claim 7
Dependent Claim
21 words
The method of claim 4 wherein said opposite level metallization pattern is formed by selective etching of said planar metallic layer.
Claim 8
Dependent Claim
41 words
The method of claim 2 further including the steps of forming on said opposite covering layer, at least one additional opposite level metallization pattern, and forming over each additional opposite level metallization pattern, an additional opposite covering layer of dielectric material.
Claim 9
Dependent Claim
54 words
The method of claim 2 including the further step of forming via holes through at lest one covering layer of dielectric material to the underlying metallization pattern prior to the formation of any additional level metallization pattern whereby the via holes provide paths from the additional level metallization pattern to the underlying metallization pattern.
Claim 10
Dependent Claim
54 words
The method of claim 6 including the further step of forming via holes through at least one covering layer of dielectric material to the underlying metallization pattern prior to the formation of any additional level metallization pattern, whereby the via holes provide paths from the additional level metallization pattern to the underlying metallization pattern.
Claim 11
Dependent Claim
51 words
The method of claim 8 including the further step of forming at least one via hole through said primary layer prior to formation of subsequent opposite level metallization patterns whereby the via hole provides a path from one of said subsequent opposite level metallization patterns to said first level metallization pattern.
Claim 12
Dependent Claim
23 words
The method of claim 9 wherein at least one of said via holes is coincident with a via hole in an underlying layer.
Claim 13
Dependent Claim
12 words
The method of claim 9 wherein said substrate is a semiconductor material.
Claim 14
Dependent Claim
11 words
The method of claim 11 wherein said semiconductor material is silicon.
Claim 15
Dependent Claim
13 words
The method of claim 12 wherein said covering layers are of silicon dioxide.
Claim 16
Dependent Claim
16 words
The method of claim 4 wherein said dielectric portion of said primary layer is silicon dioxide.
Claim 17
Dependent Claim
58 words
The method of claim 14 wherein said silicon substrate is heavily doped with conductivity-determining impurities, said primary layer is a composite of a planar metallic layer interfacing with the substrate and a planar layer of silicon dioxide at the exposed surface, and said removal of said silicon substrate with said chemical etchant is accomplished by anodic electrochemical etching.
Claim 18
Dependent Claim
14 words
The method of claim 14 wherein said deposited supporting layer is of polycrystalline silicon.
Claim 19
Dependent Claim
14 words
The method of claim 16 wherein said supporting polycrystalline silicon layer is epitaxially deposited.
Claim 20
Dependent Claim
61 words
The method of claim 16 wherein said polycrystalline silicon layer is doped with a conductivity-determining impurity and at least one via hole is formed through the covering layer beneath said polycrystalline layer prior to the deposition of said polycrystalline layer to provide a conductive path through said via hole from said polycrystalline layer to the metallization pattern under said covering layer.
Claim 21
Dependent Claim
18 words
The method of claim 8 wherein said metallization patterns and said via holes are formed by photolithographic etching.
Claim 22
Dependent Claim
64 words
The method of claim 9 including the further steps of forming a plurality of via holes through the last formed additional opposite layer of dielectric material to the underlying metallization pattern, and forming on the surface of said additional opposite layer, a plurality of solder pads having a lower melting point than and conductively connected to said underlying metallization pattern through said via holes.
Claim 23
Dependent Claim
54 words
The method of claim 20 including the further steps of placing at least one integrated circuit chip having plurality of solder pads corresponding to solder pads on said carrier whereby the corresponding pads are in contact, and heating to bond and align said chip to said carrier through the solder-reflow of said corresponding pads.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-10 | 1979-05-12 | 1979-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-10 | 1983-05-12 | 1983-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-10 | 1987-05-12 | 1987-11-11 | $7700.00 | Window Closed / Lapsed |