Semiconductor switching device

Claim 2

A SEMICONDUCTOR DEVICE COMPRISING: A BODY OF SEMICONDUCTOR MATERIAL HAVING THREE LAYERS INCLUDING AN INTERNAL LAYER OF ONE CONDUCTIVITY TYPE BOUNDED ON OPPOSITE SIDES BY TWO LAYERS OF THE OPPOSITE CONDUCTIVITY TYPE TO FORM A PLURALITY OF P-N JUNCTIONS, SAID BODY HAVING FIRST AND SECOND OPPOSED OUTER SURFACES OF SAID OPPOSITE CONDUCTIVITY TYPE, AN ARRAY OF DISCRETE REGIONS OF SAID ONE CONDUCTIVITY TYPE SPACED APART OVER SUBSTANTIALLY THE ENTIRE AREA OF SAID FIRST OUTER SURFACE OF SAID BODY, SAID DISCRETE REGIONS HAVING SYMMETRICAL CROSS SECTIONS IN PLANES PARALLEL TO SAID OUTER SURFACES AND EXTENDING INWARDLY FROM SAID FIRST OUTER SURFACE INTO THE INTERIOR OF ONE OF SAID LAYERS OF OPPOSITE CONDUCTIVITY TYPE, A LAYER OF HIGHLY DOPED SEMICONDUCTOR MATERIAL OF SAID OPPOSITE CONDUCTIVITY TYPE FORMED OVER SAID FIRST OUTER SURFACE OF SAID BODY AND EXTENDING BETWEEN AND SURROUNDING SAID DISCRETE REGIONS, A FIRST LARGE AREA ELECTRODE IN LOW RESISTANCE OHMIC CONTACT WITH THE EXPOSED SURFACES OF A PLURALITY OF SAID DISCRETE REGIONS AND WITH A PORTION OF SAID FIRST OUTER SURFACE,

Claim 3

The semiconductor device of claim 1 wherein the cross sectional areas of said regions are generally rectangular and said regions are spaced apart over the entire area of said first outer surface with thin intervals of opposite conductivity type disposed between and surrounding each of said regions.

Claim 4

The semiconductor device of claim 1 wherein the lengths of said regions along the axes thereof are disposed normal to said outer surfaces.

Claim 5

The semiconductor device of claim 1 and further comprising a groove disposed between said first and second electrodes.

Claim 6

The semiconductor device of claim 4 and further comprising an area of said one conductivity type formed in said first outer surface and having an area larger than one of said discrete regions, said area spaced on the other side of said groove from said first electrode, and being connected to said second electrode.

Claim 7

The semiconductor device of claim 1 wherein said regions are comprised of N type conductivity material.

Claim 8

The semiconductor device of claim 6 and further comprising a layer of P+ semiconductor material disposed over said first outer surface and surrounding said discrete regions, the thickness of said layer of P+ material being less than the thickness of said three layers.

Claim 9

A semiconductor device comprising: a body of semiconductor material including a plurality of interleaved layers of opposite semiconductor material type to form a plurality of P-N junctions, an array of elongated discrete regions of semiconductor material of one conductivity type formed in an exterior layer of the opposite conductivity type and extending from the external surface normally into the interior of said layer, said elongated regions having symmetrical cross sections in planes parallel to said external surface and closely spaced apart less than ten mils from one another over the surface area of said exterior layer with intervals of said opposite conductivity type disposed between and surrounding said regions, first and second electrodes contacting said exterior surface and each contacting a group of said regions and spaced apart by at least one of said intervals of said opposite conductivity type, a source of control bias connected to said second electrode, and a third electrode connected to the other exterior layer of semiconductor material of said body wherein a voltage drop occurs adjacent said regions which is normal to said outer surfaces during initial conduction of said device upon the application of a predetermined bias potential.

Claim 10

A semiconductor device comprising: a body of semiconductor material including a plurality of interleaved layers of opposite semiconductor material type to form a plurality of P-N junctions, an array of elongated discrete regions of semiconductor material of one conductivity type formed in an exterior layer of the opposite conductivity type and extending from the external surface normally into the interior of said layer, said elongated regions having symmetrical cross sections in planes parallel to said external surface and closely spaced apart less than ten mils from one another over the surface area of said exterior layer with intervals of said opposite conductivity type disposed between and surrounding said regions, first and second electrodes contacting said exterior surface and each contacting a group of said regions and spaced apart by at least one of said intervals of said opposite conductivity type, a source of control bias connected to said second electrode, and a third electrode connected to the other exterior layer of semiconductor material of said body wherein a voltage drop occurs adjacent said regions which is normal to said outer surfaces during initial conduction of said device upon the application of a predetermined bias potential.

Claim 11

The semiconductor device of claim 8 and further comprising a thin layer of semiconductor material of said opposite conductivity type disposed over said external surface and surrounding said discrete regions.

Claim 12

A semiconductor device of claim 9 wherein said thin layer of semiconductor material comprises P+ material.

Claim 13

The semiconductor device of claim 8 wherein a voltage drop occurs along the axes of said regions which is normal to said external surface during initial conduction of said device.

Claim 14

The semiconductor device of claim 8 and further comprising a groove separating said first and second electrodes.

Claim 15

The semiconductor device of claim 8 wherein the width of each of said regions is less than twenty five mils.

Claim 16

The semiconductor device of claim 8 wherein the width of each of said regions is less than ten mils.