← Back to Patent Explorer
US3634739A Expired / Lapsed US ⏱️ 0.0 years remaining

Thyristor having at least four semiconductive regions and method of making the same

Assignee: Licentia Patent Verwaltungs GmbH
•
Filing: 1970-12-02
•
Granted: 1972-01-11
•
Expires: 1990-12-02
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A thyristor having a base region shorted to an associated emitter region on one of the principal faces of the thyristor wafer, wherein there is a net impurity center concentration equal to at least 1018 impurity centers per cubic centimeter at the surface of the base region in contact with the shorting electrode, wherein there is a continual decrease of the net impurity center concentration in the base region from its value at the shorting electrode at least over the distance from the shorting electrode to the side of the emitter region farthest from the shorting electrode, and wherein there is an ohmic contact of very small contact resistance between the shorting electrode and the base region.

Inventors

  • 👤 Edgar Borchert
  • 👤 Werner Frese
  • 👤 Wolfgang Pikorz
  • 👤 Alois Sonntag

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 19:25
CPC Classifications
H; H10; H10P; H10P95/00; H10D; H10D99/00

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 26 words
A thyristor as claimed in claim 1, wherein said ohmic contact between said electrode and said base region is formed by a base layer containing gold.
Claim 2
Dependent Claim 40 words
A thyristor as claimed in claim 2, wherein said ohmic contact between said electrode and said base region is formed by a base layer of gold alloyed into the semiconductive material of the base region, the semiconductive material being silicon.
Claim 3
Dependent Claim 78 words
A thyristor as claimed in claim 2, wherein the semiconductive regions are arranged in the sequence NPNP, the N-emitter region is pierced by a plurality of channels of the P-base region, said electrode is a cathode contact short circuiting the N-emitter region with said channels, and the net acceptor concentration in the P-base region continually decreases from its value at the short circuiting cathode to its value at the PN-junction between the P-base region and the N-base region.
Claim 4
Dependent Claim 77 words
A thyristor as claimed in claim 4, further comprising a gate electrode contacting said P-base region, the material of said semiconductive regions being silicon, the cathode and the gate electrode being formed of a base layer of gold-silicon eutectic having a thickness of about 1 X 10 6 meters and, on the base layer, a vapor-deposited layer composite having a layer sequence chromium-gold-chromium, the total thickness of said layer composite being about 2 X 10 6 meters.
Claim 5
Independent Claim 139 words
A method for making a thyristor, comprising the steps of diffusing, in a first diffusion step, acceptor atoms into all sides of an N-conductive silicon wafer, diffusing, in a second diffusion step, acceptor atoms into all parts of a principal face of the wafer while simultaneously diffusing donor atoms into only some parts of said principal face for creating an N-emitter region set into a P-base region and for maintaining a net acceptor concentration on said principal face at least equal to that net acceptor concentration which existed after the first diffusion step and having a minimum value of 1018 atoms per cubic centimeter, and alloying into the silicon on said principal face in short circuiting relationship to said N-emitter region and said P-base region a layer of gold having a thickness of about 1 X 10 6 meters.
Claim 6
Dependent Claim 19 words
A method as claimed in claim 6, wherein said acceptor atoms are gallium and said donor atoms are phosphorus.
Claim 7
Dependent Claim 24 words
A method as claimed in claim 7, wherein gallium phosphide is the source for said acceptor and donor atoms in the second diffusion step.

References Cited (Backward Citations)

US3274460A Cited
US3277352A Cited
US3556878A Cited
US3566210A Cited
US3476992A Cited
US3486088A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-01-10 1975-07-12 1976-01-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-01-10 1979-07-12 1980-01-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-01-10 1983-07-12 1984-01-11 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag