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US3917962A Expired / Lapsed US ⏱️ 0.0 years remaining

Synchronous switching circuit

Assignee: Grigsby Barton Inc
•
Filing: 1974-03-04
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Granted: 1975-11-04
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Expires: 1994-03-04
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Abstract

Abstract A switching circuit for controlling the application of an a.c. source to a load employs a detector for triggering a control thyristor at a zero-voltage crossing of the a.c. source and means for supplying a latch current to the gate of the control thyristor during succeeding cycles of the a.c. source. The control thyristor is employed to latch a switching thyristor which, in turn, applies the power from the a.c. source to the load. The detector includes a transistor with a switching means connected between the transistor control terminal and one of the load terminals and biased so that the transistor is normally conductive when the switching means is open circuited to thereby shunt current away from the gate terminal of the control thyristor. When the switching means is conductive, the transistor is biased to be rendered non-conductive when the a.c. source voltage passes through zero and thereby applies current to the gate terminal of the control thyristor.

Inventors

  • 👤 Joseph E Pascente

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 20:17
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/13; H03K17/136; Y; Y10; Y10S; Y10S323/00; Y10S323/902

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 368 words
In a circuit for selectively triggering a control thyristor having anode, cathode and gate terminals, at the zero crossing of the voltage of an a.c. source, comprising a full-wave rectifier circuit having input terminals for operable connection thereof to the a.c. source, a zero-voltage crossing detector circuit having load terminals for connection across the anode and cathode of the control thyristor and across the output of said rectifier circuit and including a transistor having a control terminal and a pair of load terminals for controlling the application of current from one of said load terminals to the gate terminal of the control thyristor, said transistor conducting current through said load terminals to thereby shunt current away from said gate terminal when the transistor is in its conductive state, and permitting the flow of current at said gate terminal of the control thyristor for triggering the same when said transistor is in its non-conductive state, and switching means connected between the control terminal and the other of said load terminals of said transistor for continuously maintaining said transistor in conduction when said switching means is non-conductive, the improvement wherein said zero-voltage crossing detector circuit includes a first resistor connected between the anode of the control thyristor and said one load terminal of said transistor, a second resistor connected between the anode of the control thyristor and the control terminal of said transistor, a third resistor series connected with said switching means between said control terminal and said other load terminal of said transistor, said second and third resistors defining a voltage divider for applying a voltage to the control terminal of said transistor such that it is biased to its non-conductive state when said a.c. source voltage passes through zero and when said switching means is conductive, said transistor thereby providing an output pulse to the gate terminal of the control thyristor corresponding to the zero-voltage crossing of the a.c. source and the control thyristor being latched in a conductive state by current flow through said first resistor coupled between the gate and anode of the thyristor so long as said transistor remains nonconductive, said transistor being the sole three terminal transistor device in said zero-voltage crossing detector circuit.
Claim 2
Dependent Claim 368 words
In a circuit for selectively triggering a control thyristor having anode, cathode and gate terminals, at the zero crossing of the voltage of an a.c. source, comprising a full-wave rectifier circuit having input terminals for operable connection thereof to the a.c. source, a zero-voltage crossing detector circuit having load terminals for connection across the anode and cathode of the control thyristor and across the output of said rectifier circuit and including a transistor having a control terminal and a pair of load terminals for controlling the application of current from one of said load terminals to the gate terminal of the control thyristor, said transistor conducting current through said load terminals to thereby shunt current away from said gate terminal when the transistor is in its conductive state, and permitting the flow of current at said gate terminal of the control thyristor for triggering the same when said transistor is in its non-conductive state, and switching means connected between the control terminal and the other of said load terminals of said transistor for continuously maintaining said transistor in conduction when said switching means is non-conductive, the improvement wherein said zero-voltage crossing detector circuit includes a first resistor connected between the anode of the control thyristor and said one load terminal of said transistor, a second resistor connected between the anode of the control thyristor and the control terminal of said transistor, a third resistor series connected with said switching means between said control terminal and said other load terminal of said transistor, said second and third resistors defining a voltage divider for applying a voltage to the control terminal of said transistor such that it is biased to its non-conductive state when said a.c. source voltage passes through zero and when said switching means is conductive, said transistor thereby providing an output pulse to the gate terminal of the control thyristor corresponding to the zero-voltage crossing of the a.c. source and the control thyristor being latched in a conductive state by current flow through said first resistor coupled between the gate and anode of the thyristor so long as said transistor remains nonconductive, said transistor being the sole three terminal transistor device in said zero-voltage crossing detector circuit.
Claim 3
Dependent Claim 40 words
The circuit of claim 1 wherein said control thyristor comprises a silicon controlled rectifier and said switching means comprises a normally non-conductive opto-electronic relay that becomes conductive in response to the application of a command signal at the input thereof.
Claim 4
Dependent Claim 27 words
The circuit of claim 1 wherein said transistor has a forward voltage drop acrOss its load terminal circuit of an order no greater than approximately 70 millivolts.
Claim 5
Dependent Claim 27 words
The circuit of claim 1 further comprising a Zener diode connected across the load terminals of said transistor to limit the magnitude of the voltage developd thereacross.
Claim 6
Dependent Claim 45 words
A circuit as defined in claim 2 wherein said opto-electronic relay comprises a light emitting diode energizable responsive to receiving said command signal and a phototransistor optically coupled to said light emitting diode and becoming conductive when said command signal energizes said light emitting diode.
Claim 7
Dependent Claim 28 words
A circuit as defined in claim 5 wherein said phototransistor has its collector emitter path connected between said third resistor and said other load terminal of said transistor.
Claim 8
Dependent Claim 20 words
A circuit as defined in claim 1 wherein a phase shifting capacitor is connected in parallel across said third resistor.

References Cited (Backward Citations)

US3328606A Cited
US3648075A Cited
US3723769A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-11-03 1979-05-05 1979-11-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-11-03 1983-05-05 1983-11-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-11-03 1987-05-05 1987-11-04 $7700.00 Window Closed / Lapsed

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