Resynchronizable phase-encoded recording

Claim 2

A multitrack digital signal recorder having a transducer for each track for recording signals on a record medium having longitudinal edges parallel to record tracks on said medium, circuit means for exchanging data signals with said transducers as parallel bytes of signals, one signal exchanged through each transducer for each byte, the improvement including in combination: means indicating that a given number of bytes has been exchanged with said transducers; an odd/even counter; and resynchronization means responsive to said indicating means and to said odd/even counter to perform a resynchronization operation with respect to said recorder of a first type when said odd/even counter is indicating an even count and of a second type when said odd/even counter is indicating an odd type, said first and second types of resynchronization operations yielding a different resynchronization capability with respect to predetermined ones of said tracks.

Claim 3

The digital signal recorder set forth in claim 1 for a phase-encoded record system wherein said resynchronization means includes: first means for exchanging successive zero signals between said transducers and said resynchronization means operatively associated with tracks adjacent longitudinal edges of said record medium; and resynchronization second means for selectively exchanging all-0 signals on all-1 signals between said transducers for respective ones of said predetermined tracks and said resynchronization means, none of said predetermined tracks being adjacent a longitudinal edge of said record medium.

Claim 4

The digital signal recorder set forth in claim 2 having a parity track centrally between said longitudinal edges and further including in combination: said resynchronization means includes even resync means for employing successive 1 signals with respect to said parity track and all-0 signals with respect to another one of said other predetermined tracks; odd sync means in said synchronization means for employing successive 0 signals with respect to said parity track and successive 1 signals with respect to said one other track; said even and odd resync means respectively performing said first and second types of resynchronization operations.

Claim 5

The digital signal recorder set forth in claim 3 further including in combination: a byte counter having a plurality of output signals indicating at least two ranges of byte counts, one of said ranges indicating transferring data signals and a second of said ranges indicating transferring predetermined resynchronization signals; said first and second means being responsive to said byte counter second range signal for exchanging their said respective signals; and additional means responsive to a last numerical value of said byte counter for exchanging all 1''s with all transducers for all said tracks of said medium irrespective of said odd/even counter.

Claim 6

The digital signal recorder set forth in claim 2 wherein said first means exchanges successive 0 signals only to outermost tracks adjacent said longitudinal edges; said second means including means for exchanging successive 1 signals with an odd number greater than one of said tracks intermediate said outermost tracks and means for supplying successive 0 signals to all other ones of said tracks; means in said second means responsive to said odd/even counter for selectively reversing which ones of said other ones of said tracks have sUccessive 1 and 0 signals exchanged therewith, respectively; and means for recording all-1 signals of one byte in all of said tracks after said successive 1 and 0 signals.

Claim 7

The digital signal set forth in claim 1 wherein said resync means includes means to exchange successive 1 signals with an odd plurality of said other tracks, while said other means exchanges successive 0 signals with all remaining tracks; and further means responsive to said odd/even counter to exchange successive 1 signals with said remaining tracks except for ones of said tracks immediately adjacent said longitudinal edges.

Claim 8

The digital signal recorder of claim 1 for phase-encoded recording and wherein said resync means includes in combination: a byte counter having ranges of count states indicating data signal exchange, resynchronization signal exchange, and marker signal exchange; a first AND circuit responsive to said marker signal count state for supplying an output signal resulting in all-1''s signal byte being exchanged with all tracks and receiving inputs from at least said byte counter for exchanging said all-1''s signal byte at least once for said resync pattern; a second AND circuit responsive to said byte counter indicating said resynchronization signal exchange states for activating exchange of a succession of 0 signals with predetermined ones of said tracks including two tracks adjacent said longitudinal edges, respectively; third AND circuit means responsive to said byte counter resynchronization signal exchange states and to said odd/even counter to activate exchanging a succession of 0 signals with certain ones of said tracks intermediate said outermost tracks and for exchanging 1 signals with predetermined ones of said other tracks, said predetermined number of tracks being odd; and fourth AND circuit means responsive to said byte counter being in said resynchronization signal exchange states and said odd/even counter to actuate exchange of successive 0 signals with certain ones of said tracks intermediate said outermost tracks and for actuating exchanging successive 1 signals with an odd number of given ones of said tracks, the number of given tracks being odd and none of the given tracks being said predetermined tracks.

Claim 9

The digital signal recorder set forth in claim 7 wherein said first AND circuit means is responsive to said byte counter marker signal states to record all 1''s at the beginning byte position and at the ending byte position of each and every resync pattern.

Claim 10

A multitrack digital signal recorder having a transducer for each track, circuit means for exchanging data signals with said transducers as bytes of signals, one signal with each of said tracks for each byte, said tracks being on a record medium with two of said tracks being adjacent longitudinal edges, respectively, and being termed outer tracks, the improvement including in combination: means indicating that a given number of bytes have been exchanged with said transducers; and resynchronization means responsive to said indicating means for effecting a resynchronization operation having first and second characteristics, said resync operations with said first and second characteristics being applied alternately and successively.

Claim 11

A multitrack digital signal recorder having a transducer for each track, circuit means for exchanging data signals with said transducers as bytes of signals, one signal with each of said tracks for each byte, said tracks being on a record medium with two of said tracks being adjacent longitudinal edges, respectively, and being termed outer tracks, the improvement including in combination: means indicating that a given number of bytes have been exchanged with said transducers; and resynchronization means responsive to said indicating means for effecting a resynchronization operation having first and second characteristics, said resync operations with said first and second characteristics being applied alternately and successively.

Claim 12

The digital signal recorder set forth in claim 9 wherein: said first resynchronization characteristic comprises resynchronization operations with respect to all said tracks excepting at least a first given one track other than said outer tracks; and said second resynchronization characteristic comprises resynchronization operations with respect to all said tracks excepting at least a second given one track other than said outer track and said first given one track.

Claim 13

The digital signal recorder set forth in claim 9 wherein said first given and second given ones of said tracks each comPrise an odd number of tracks greater than one.

Claim 14

The digital signal recorder set forth in claim 11 further including in combination: bistable means indicating said first and second characteristics; and means responsive to said resynchronization operations exhibiting said first and second characteristics to alter said bistable means.

Claim 15

The digital signal recorder set forth in claim 11 further including means indicating exchange of successive 1''s and 0''s signals with said tracks; a combining circuit responsive to said successive 1 or 0 exchange to supply a control signal; and mode control means responsive to said control signal to actuate said resynchronization means to effect at least one of said resynchronization operations to exhibit either said first or second characteristics.