Shifting apparatus for automatic data alignment

Claim 2

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the left for storing right aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binaRy the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for right shifting the type fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means left shifting the right justified byte field input from said processor register in a write operation by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; whereby multiple byte data fields can be transferred between the processor and memory unit under the control of a minimum number of control words.

Claim 3

The information processing system of claim 1, which further comprises: a read formatting means having a data input connected to said length register and a control input connected to said control word register, for inserting zeros in the number of leftmost byte fields equal to 2N-1 minus the value of length register contents, for the byte fields read from said memory, in accordance with said control words; whereby all necessary byte masking is accomplished for the leftmost bytes in the right justified byte fields read from said memory unit.

Claim 4

The information processing system of claim 1, which further comprises: a write formatting means having a data input connected to said pointer register and a data input connected to said sum output of said binary adder, for identifying the group of contiguous byte lines on said memory bus between the byte field number equal to the value of said sum and the byte field number equal to the value of said pointer, over which bytes are to be written into said memory unit; whereby less than 2N contiguous bytes are selectively written into said memory.

Claim 5

The information processing system of claim 1 which further comprises: a control word branch unit having a control input connected to said carry output of said binary adder and a data input connected to said control word register; a control word storage having an input connected to said branch unit and an output connected to said control word register; a first gate means for conditionally connecting the input of said length register to said sum output of said binary adder when a carry signal occurs indicating the accessing of a multibyte field which lies in two contiguous words of said memory; a second gate means for conditionally setting the input of said pointer register to zero when said carry signal occurs; said branch unit responsive to said carry signal from said binary adder to access from said control word storage a second control word which is loaded in said control word register to initiate the accessing of the second portion of said multibyte field in the rightmost of said two memory words; said sum output loaded into said length register representing the length of said second portion of said multibyte field; whereby a multibyte field can be written across a memory word boundary in said memory unit under the control of two control words.

Claim 6

The information processing system of claim 4, which further comprises: a cross boundary formattng means having a control input connected to said control word register, a data input connected to said length register, and an output connected to said shifting means, to conditionally reset byte fields numbered 2N-1 minus the value of contents in the length register to 2N-1, in said shIfting means in response to said second control word when a memory read is specified; said second control word specifying that said read formatting means be inoperative during the accessing of said second memory word so that the byte fields accessed therefrom are loaded into said shifting means without disturbing the byte fields accessed from said first memory word; whereby a multibyte field can be read from two contiguous memory words and be stored right justified in said processor register under the control of two control words.

Claim 7

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access structured memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the left for storing right aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control was register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for right shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means left shifting the right justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; a read formatting means having a data input connected to said length register and a control input connected to said control word register, for inserting zeros in the number of leftmost byte fields equal to 2N-1 minus the value of length register contents, for the byte fields read from said memory, in accordance with said control words; a write formatting means having a data input connected to said pointer register and a data input connected to said sum output of said binary adder, for identifying the group of contiguous byte lines on said memory bus between the byte field number equal to value of said sum and the byte field number equal to value of said pointer, over which bytes are to be written into said memory unit; whereby less than 2N contiguous bytes can be selectively written into said memory under the control of a single control word.

Claim 8

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access structured memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the left for storing right aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control was register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for right shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means left shifting the right justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; a read formatting means having a data input connected to said length register and a control input connected to said control word register, for inserting zeros in the number of leftmost byte fields equal to 2N-1 minus the value of length register contents, for the byte fields read from said memory, in accordance with said control words; a write formatting means having a data input connected to said pointer register and a data input connected to said sum output of said binary adder, for identifying the group of contiguous byte lines on said memory bus between the byte field number equal to value of said sum and the byte field number equal to value of said pointer, over which bytes are to be written into said memory unit; whereby less than 2N contiguous bytes can be selectively written into said memory under the control of a single control word.

Claim 9

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access structured memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the left for storing right aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means Connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for right shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means left shifting the right justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; a write formatting means having a data input connected to said pointer register and a data input connected to said sum output of said binary adder, for identifying the group of contiguous byte lines on said memory bus between the byte field number equal to value of said sum and the byte field number equal to value of said pointer, over which bytes are to be written into said memory unit; a control word branch unit having a control input connected to said carry output of said binary adder and a data input connected to said control word register; a control word storage having an input connected to said branch unit and an output connected to said control word register; a first gate means for conditionally connecting the input of said length register to said sum output of said binary adder when a carry signal occurs indicating the accessing of a multibyte field which lies in two continguous words of said memory; a second gate means for conditionally setting the input of said pointer register to zero when said carry signal occurs; said branch unit responsive to said carry signal from said binary adder to access from said control word storage a second control word which is loaded in said control word register to initiate the accessing of the second portion of said multibyte field in the rightmost of said two memory words; said sum output loaded into said length register representing the length of said second portion of said multibyte field; whereby a multibyte field can be written across a memory word boundary in said memory unit under the control of two control words.

Claim 10

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access structured memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the left for storing right aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means Connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for right shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means left shifting the right justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; a write formatting means having a data input connected to said pointer register and a data input connected to said sum output of said binary adder, for identifying the group of contiguous byte lines on said memory bus between the byte field number equal to value of said sum and the byte field number equal to value of said pointer, over which bytes are to be written into said memory unit; a control word branch unit having a control input connected to said carry output of said binary adder and a data input connected to said control word register; a control word storage having an input connected to said branch unit and an output connected to said control word register; a first gate means for conditionally connecting the input of said length register to said sum output of said binary adder when a carry signal occurs indicating the accessing of a multibyte field which lies in two continguous words of said memory; a second gate means for conditionally setting the input of said pointer register to zero when said carry signal occurs; said branch unit responsive to said carry signal from said binary adder to access from said control word storage a second control word which is loaded in said control word register to initiate the accessing of the second portion of said multibyte field in the rightmost of said two memory words; said sum output loaded into said length register representing the length of said second portion of said multibyte field; whereby a multibyte field can be written across a memory word boundary in said memory unit under the control of two control words.

Claim 11

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the left for storing right aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storaGe address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for right shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means left shifting the right justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; a read formatting means having a data input connected to said length register and a control input connected to said control word register, for inserting zeros in the number of leftmost byte fields equal to 2N-1 minus the value of length register contents, for the byte fields read from said memory, in accordance with said control words; a control word branch unit having a control input connected to said carry output of said binary adder and a data input connected to said control word register; a control word storage having an input connected to said branch unit and an output connected to said control word register; a first gate means for conditionally connecting the input of said length register to said sum output of said binary adder when a carry signal occurs indicating the accessing of a multibyte field which lies in two contiguous words of said memory; a second gate means for conditionally setting the input of said pointer register to zero when said carry signal occurs; said branch unit responsive to said carry signal from said binary adder to access from said control word storage a second control word which is loaded in said control word register to initiate the accessing of the second portion of said multibyte field in the rightmost of said two memory words; said sum output loaded into said length register representing the length of said second portion of said multibyte field; a cross boundary formatting means having a control input connected to said control word register, a data input connected to said length register, and an output connected to said shifting means, to conditionally reset byte fields numbered 2N-1 minus the value of contents in length register to 2N-1, in said shifting means in response to said second control word when a memory read is specified; said second control word specifying that said read formatting means be inoperative during the accessing of said second memory word so that the byte fields accessed therefrom are loaded into said shifting means without disturbing the byte fields accessed from said first memory word; whereby a multibyte field can be read from two contiguous memory words and be stored right justified in said processor register under the control of two control words.

Claim 12

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the left for storing right aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storaGe address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for right shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means left shifting the right justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; a read formatting means having a data input connected to said length register and a control input connected to said control word register, for inserting zeros in the number of leftmost byte fields equal to 2N-1 minus the value of length register contents, for the byte fields read from said memory, in accordance with said control words; a control word branch unit having a control input connected to said carry output of said binary adder and a data input connected to said control word register; a control word storage having an input connected to said branch unit and an output connected to said control word register; a first gate means for conditionally connecting the input of said length register to said sum output of said binary adder when a carry signal occurs indicating the accessing of a multibyte field which lies in two contiguous words of said memory; a second gate means for conditionally setting the input of said pointer register to zero when said carry signal occurs; said branch unit responsive to said carry signal from said binary adder to access from said control word storage a second control word which is loaded in said control word register to initiate the accessing of the second portion of said multibyte field in the rightmost of said two memory words; said sum output loaded into said length register representing the length of said second portion of said multibyte field; a cross boundary formatting means having a control input connected to said control word register, a data input connected to said length register, and an output connected to said shifting means, to conditionally reset byte fields numbered 2N-1 minus the value of contents in length register to 2N-1, in said shifting means in response to said second control word when a memory read is specified; said second control word specifying that said read formatting means be inoperative during the accessing of said second memory word so that the byte fields accessed therefrom are loaded into said shifting means without disturbing the byte fields accessed from said first memory word; whereby a multibyte field can be read from two contiguous memory words and be stored right justified in said processor register under the control of two control words.

Claim 13

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memory unit for addressing words stored therein; a processor unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the right for storing left aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input Connected to said control word register; a length register connected to said control word register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for left shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means right shifting the left justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word. whereby multiple byte data fields can be transferred between the processor and memory unit under the control of a minimum number of control words.

Claim 14

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memory unit for addressing words stored therein; a processor unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the right for storing left aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input Connected to said control word register; a length register connected to said control word register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for left shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means right shifting the left justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word. whereby multiple byte data fields can be transferred between the processor and memory unit under the control of a minimum number of control words.

Claim 15

The information processing system of claim 9, which further comprises: a read formatting means having a data input connected to said length register and a control input connected to said control word register, for inserting zeros in the number of rightmost byte fields equal to 2N-1 minus the value of length register contents, for the byte fields read from said memory, in accordance with said control words; whereby all necessary byte masking is accomplished for the righmost bytes in the left justified byte fields read from said memory unit.

Claim 16

The information processing system of claim 9, which further comprises: a write formatting means having a data input connected to said pointer register and a data input connected to said sum output of said binary adder, for identifying the group of contiguous byte lines on said memory bus between the byte field number equal to value of said sum and the byte field number equal to value of said pointer, over which bytes are to be written into said memory unit; whereby less than 2N contiguous bytes are selectively written into said memory.

Claim 17

The information processing system of claim 9 which further comprises: a control word branch unit having a control input connected to said carry output of said binary adder and a data input connected to said control word register; a control word storage having an input connected to said branch unit and an output connected to said control word register; a first gate means for conditionally connecting the input of said length register to said sum output of said binary adder when a carry signal occurs indicating the accessing of a multibyte field which lies in two contiguous words of said memory; a second gate means for conditionally setting the input of said pointer register to zero when said carry signal occurs; said branch unit responsive to said carry signal from said binary adder to access from said control word storage a second control word which is loaded in said control word register to initiate the accessing of the second portion of said multibyte field in the leftmost of said two memory words; said sum output loaded into said length register representing the length of said second portion of said multibyte field; whereby a multibyte field can be written across a memory word boundary in said memory unit under the control of two control words.

Claim 18

The information processing system of claim 12, which further comprises: a cross boundary formatting means having a control input connected to said control word register, a data input connected to said length register, and an output connected to said shifting means, to conditionally reset bytE fields numbered 2N-1 minus the value of contents in length register to 2N-1, in said shifting means in response to said second control word when a memory read is specified; said second control word specifying that said read formatting means be inoperative during the accessing of said second memory word so that the byte fields accessed therefrom are loaded into said shifting means without disturbing the byte fields accessed from said first memory word; whereby a multibyte field can be read from two contiguous memory words and be stored left justified in said processor register under the control of two control words.

Claim 19

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the right for storing left aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for left shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means right shifting the left justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; a read formatting means having a data input connected to said length register and a control input connected to said control word register, for inserting zeros in the number of rightmost byte fields equal to 2N-1 minus the value of length register contents, for the byte fields read from said memory, in accordance with said control words; a write formatting means having a data input connected to said pointer register and a data input connected to said sum output of said binary adder, for identifying the group of contiguous byte lines on said memory bus between the byte field number equal to value of said sum and the byte field number equal to value of said pointer, over which bytes are to be written into said memory unit; whereby less than 2N contiguous bytes can be selectively written into said memory under the control of a single control word.

Claim 20

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the right for storing left aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for left shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means right shifting the left justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; a read formatting means having a data input connected to said length register and a control input connected to said control word register, for inserting zeros in the number of rightmost byte fields equal to 2N-1 minus the value of length register contents, for the byte fields read from said memory, in accordance with said control words; a write formatting means having a data input connected to said pointer register and a data input connected to said sum output of said binary adder, for identifying the group of contiguous byte lines on said memory bus between the byte field number equal to value of said sum and the byte field number equal to value of said pointer, over which bytes are to be written into said memory unit; whereby less than 2N contiguous bytes can be selectively written into said memory under the control of a single control word.

Claim 21

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the right for storing left aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for left shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means right shifting the left justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; a write formatting means having a data input connected to said pointer register and a data input connected to said sum output of said binary adder, for identifying the group of contiguous byte lines on said memory bus between the byte field number equal to value of said sum and the byte field number equal to value of said pointer, over which bytes are to be written into said memory unit; a control word branch unit having a control input connected to said carry output of said binary adder and a data input connected to said control word register; a control word storage having an input connected to said branch unit and an output connected to said control word register; a first gate means for conditionally connecting the input of said length register to said sum output of said binary adder when a carry signal occurs indicating the accessing of a multibyte field which lies in two contiguous words of said memory; a second gate means for conditionally setting the input of said pointer register to zero when said carry signal occurs; said branch unit responsive to said carry signal from said binary adder to access from said control word storage a second control word which is loaded in said control word register to initiate the accessing of the second portion of said multibyte field in the leftmost of said two memory words; said sum output loaded into said length register representing the length of said second portion of said multibyte field; whereby a multibyte field can be written across a memory word boundary in said memory unit under the control of two control words.

Claim 22

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memory unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the right for storing left aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binary the value of one less than the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for left shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said shifting means right shifting the left justified byte field input from said processor register in a write operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; a write formatting means having a data input connected to said pointer register and a data input connected to said sum output of said binary adder, for identifying the group of contiguous byte lines on said memory bus between the byte field number equal to value of said sum and the byte field number equal to value of said pointer, over which bytes are to be written into said memory unit; a control word branch unit having a control input connected to said carry output of said binary adder and a data input connected to said control word register; a control word storage having an input connected to said branch unit and an output connected to said control word register; a first gate means for conditionally connecting the input of said length register to said sum output of said binary adder when a carry signal occurs indicating the accessing of a multibyte field which lies in two contiguous words of said memory; a second gate means for conditionally setting the input of said pointer register to zero when said carry signal occurs; said branch unit responsive to said carry signal from said binary adder to access from said control word storage a second control word which is loaded in said control word register to initiate the accessing of the second portion of said multibyte field in the leftmost of said two memory words; said sum output loaded into said length register representing the length of said second portion of said multibyte field; whereby a multibyte field can be written across a memory word boundary in said memory unit under the control of two control words.

Claim 23

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memroy unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the right for storing left aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binary the value of one less tHan the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for left shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said sum output loaded into said length register representing the length of said second portion of said multibyte field; a cross boundary formatting means having a control input connected to said control word register, a data input connected to said length register, and an output connected to said shifting means, to conditionally reset byte fields numbered 2N-1 minus the value of contents in length register to 2N-1, in said shifting means in response to said second control word when a memory read is specified; said second control word specifying that said read formatting means be inoperative during the accessing of said second memory word so that the byte fields accessed therefrom are loaded into said shifting means without disturbing the byte fields accessed from said first memory word; whereby a multibyte field can be read from two contiguous memory words and be stored left justified in said processor register under the control of two control words.

Claim 24

An information processing system, comprising: a random access structured memory unit addressable in words of 2N bytes; a storage address register connected to said random access memroy unit for addressing words stored therein; a processing unit having a processor register having 2N byte fields numbered 0 to 2N-1 from the right for storing left aligned data and a control unit having a control word register for storing a control word specifying a read or write operation and the byte length of the field to be accessed in said memory unit; a shifting means connected to said processor register by a 2N byte wide processor bus and connected to said memory unit by a 2N byte wide memory bus and having a read/write control input connected to said control word register; a length register connected to said control word register for storing in binary the value of one less tHan the byte length of the field to be accessed in said memory unit; a pointer register connected to said storage address register for storing the N low order binary bits of a storage address; an N-bit binary adder connected to said length register and said pointer register, and having an N-bit sum output and a carry output, for adding the contents of the length register to the contents of the pointer register; said shifting means having an input connected to said sum output of said binary adder, for left shifting the byte fields accessed from said memory unit in a read operation, by a number of bytes equal to 2N-1 minus the value of said sum, in accordance with said control word; said sum output loaded into said length register representing the length of said second portion of said multibyte field; a cross boundary formatting means having a control input connected to said control word register, a data input connected to said length register, and an output connected to said shifting means, to conditionally reset byte fields numbered 2N-1 minus the value of contents in length register to 2N-1, in said shifting means in response to said second control word when a memory read is specified; said second control word specifying that said read formatting means be inoperative during the accessing of said second memory word so that the byte fields accessed therefrom are loaded into said shifting means without disturbing the byte fields accessed from said first memory word; whereby a multibyte field can be read from two contiguous memory words and be stored left justified in said processor register under the control of two control words.