Bucket brigade circuit having frequency dependent attenuation compensation

Claim 1

An improved bucket-brigade circuit of the type wherein there is provided a plurality of stages, each stage comprising a transistor and a capacitor coupled between the gate and drain electrodes of said transistor and wherein each stage is coupled in series such that the drain electrode of said transistor is coupled to the source electrode of the next successive transitor, and wherein the gate electrodes of odd-numbered transistors are coupled to a first clock signal and the gate electrodes of evennumbered transistors are coupled to a second clock signal having a frequency equal to that of said first clock signal and whose effective pulses occur during the intervals between the effective pulses of said first clock signal, wherein the improvement comprises: an amplifier for providing frequency dependent compensation of the signal attenuation, said amplifier comprising: a first source of voltage; a first transistor having a source electrode coupled to ground, a drain coupled to said first source and a gate electrode coupled to the drain electrode of a transistor in one of said stages; a first capacitor coupled to the drain electrode of said first transistor; a second capacitor coupled in series with said first capacitor and coupled to the drain electrode of the transistor in said one of said stages; a second source of voltage; a source of an auxiliary clock signal; and a switching transistor having a source coupled to said second source of voltage, a drain coupled to the junction of said first and second capacitors and a gate electrode coupled to said auxiliary clock signal for blocking said switching transistor when the transistor in said one of said stages is not blocked.