Integrated logical circuit device

Claim 2

The combination comprising: a first semiconductor integrated circuit device including a logical circuit, an external terminal, and a floating switching means for causing the logical level of said external terminal to respond to the output of said logical circuit during a first prescribed time interval; a secoNd semiconductor integrated circuit device including a logical circuit, an external terminal, and a floating switching means for causing the logical level of said external terminal thereof to respond to the output of said logical circuit thereof during a second prescribed time interval; and a conductor electrically connecting the external terminals of said first and second devices together, whereby the output signals of said first and second devices are conducted on the single conductor while being separated from each other in time.

Claim 3

The combination comprising: a first semiconductor integrated circuit device including a first external terminal, a first logical circuit, and a first floating switching means having an input terminal connected to the output of said first logical circuit, an output terminal connected to said first external terminal and a control terminal to which a control signal is applied, so that a circuit path is provided during a first time interval and is not provided during a second interval between its input and output terminals, a second semiconductor integrated circuit device including a second external terminal, a second logical circuit, and a second floating switching means having an input terminal connected to the output of said second logical circuit, an output terminal connected to said second external terminal and a control terminal to which a control signal is applied, so that a circuit path is provided during said second interval and is not provided during said first time interval between its input and output terminals, and a conductor electrically connecting said first and second external terminals together, said first device further including a third logical circuit and a third switching means for providing a circuit path during said second time interval and not providing a circuit path during said first time interval between said external terminals and an input of said third logical circuit, whereby signals corresponding to the output signals of said first and second logical circuit separately appear on the single conductor during said first and second time intervals, and only the signal which corresponds to the output signal of said second logical circuit is supplied to the input of said third logical circuit during said second time interval.

Claim 4

The combination comprising: a first semiconductor integrated circuit device including a first external terminal, a first logical circuit, and a first floating switching means having an input terminal connected to the output of said first logical circuit, an output terminal connected to said first external terminal and a control terminal to which a control signal is applied, so that a circuit path is provided during a first time interval and is not provided during a second interval between its input and output terminals, a second semiconductor integrated circuit device including a second external terminal, a second logical circuit, and a second floating switching means having an input terminal connected to the output of said second logical circuit, an output terminal connected to said second external terminal and a control terminal to which a control signal is applied, so that a circuit path is provided during said second interval and is not provided during said first time interval between its input and output terminals, and a conductor electrically connecting said first and second external terminals together, said first device further including a third logical circuit and a third switching means for providing a circuit path during said second time interval and not providing a circuit path during said first time interval between said external terminals and an input of said third logical circuit, whereby signals corresponding to the output signals of said first and second logical circuit separately appear on the single conductor during said first and second time intervals, and only the signal which corresponds to the output signal of said second logical circuit is supplied to the input of said third logical circuit during said second time interval.

Claim 5

The combination according to claim 2, wherein the signal which corresponds to the output signal of said first logical circuit is supplied to another input of said third logical circuit.

Claim 6

The combination according to claim 2, wherein the output signal of said first logical circuit is supplied to another input of third logical circuit.

Claim 7

The combination according to claim 4, wherein each of said first and second logical circuits is a ratioless type logical circuit.

Claim 8

The combination according to claim 2, wherein said first integrated circuit device further includes fourth switching means providing a circuit path during said first time interval and not providing a circuit path during said second time interval between said external terminals and another input of said third logical circuit, whereby only the signal corresponding to the output signal of said first logical circuit is supplied to said another input of said third logical circuit during said first time interval.

Claim 9

The combination according to claim 6, wherein each of said first and second logical circuits is a ratioless type logical circuit.

Claim 10

The combination according to claim 2, wherein said second integrated circuit device further includes a fourth logical circuit and fourth switching means for providing a circuit path during said first time interval and not providing a circuit path during said second time interval between said external terminals and an input of said fourth logical circuit, whereby only the signal which corresponds to the output signal of said first logical circuit is supplied to the input of said fourth logical circuit during said first time interval.

Claim 11

The coMbination according to claim 8, wherein the signal which corresponds to the output signal of said second logical circuit is supplied to another input of said fourth logical circuit.

Claim 12

The combination according to claim 8, wherein the output signal of said second logical circuit is supplied to another input of said fourth logical circuit.

Claim 13

The combination according to claim 10, wherein each of said first and second logical circuits is a ratioless type logical circuit.

Claim 14

The combination according to claim 8, wherein said second integrated circuit device further includes fifth switching means providing a circuit path during said second time interval and not providing a circuit path during said first time interval between said externals and another input of said fourth logical circuit, whereby only the signal which corresponds to the output signal of said second logical circuit is supplied to said another input of said fourth logical circuit during said second time interval.

Claim 15

The combination according to claim 12, wherein each of said first and second logical circuits is a ratioless type logical circuit.

Claim 16

The combination according to claim 8, wherein said first and second time intervals are defined by two-phase clock pulses for periodically operating said switching means.

Claim 17

The combination according to claim 14, wherein each of said third and fourth logical circuit includes means for storing the signal applied to the input thereof.

Claim 18

The combination according to claim 2, wherein said first and second intervals are defined by two-phase clock pulses for periodically operating said switching means.

Claim 19

The combination according to claim 16, wherein said third logical circuit includes means for storing the signal applied to the input thereof.

Claim 20

The combination according to claim 2, wherein each of said first and second floating switching means comprises first and second pairs of metal-oxide-semiconductor field-effect transistors connected in series between the terminals of a power source, the transistors of said first pair being P-channel type and the transistors of said second pair being N-channel type, the gate and drain electrodes of one of the transistors of each pair being respectively connected in common to the input and output terminals of the switching means, and the gate electrode of the other transistor of each respective pair being connected to receive said control signal which consists of a pulse and its complement pulse, so that said other transistors are simultaneously conducting or nonconducting, so as to provide or block a circuit path between the input and output terminals of the floating switching means.

Claim 21

In an integrated logic circuit including first and second integrated circuit devices, each of which includes a logic circuit and an external terminal, the improvement wherein said first integrated circuit device includes first floating switching means, having an input terminal coupled to the logic circuit of said first integrated circuit device, an output terminal connected to the external terminal of said first integrated circuit device, and a control terminal to which a control signal is applied, for providing a circuit path therethrough between the input and output terminals thereof during a first time interval and for inhibiting said circuit path during a second time interval; said second integrated circuit device includes second floating switching means having an input terminal coupled to the logic circuit of a second integrated circuit device, an output terminal connected to the external terminal of said second integrated circuit device, and a control terminal to which a control signal is applied, for inhibiting a circuit path therethrough between the input and output terminals thereof during said first time interval and for providing a circuit path therethrough between the input and output terminals thereof during said second time interval; and wherein the external terminalS of said first and second integrated circuit devices are electrically connected to each other by way of a conductor, whereby signals corresponding to the outputs of said logic circuits of said first and second integrated circuit devices separately appear on said conductor during said first and second time intervals.

Claim 22

In an integrated logic circuit including first and second integrated circuit devices, each of which includes a logic circuit and an external terminal, the improvement wherein said first integrated circuit device includes first floating switching means, having an input terminal coupled to the logic circuit of said first integrated circuit device, an output terminal connected to the external terminal of said first integrated circuit device, and a control terminal to which a control signal is applied, for providing a circuit path therethrough between the input and output terminals thereof during a first time interval and for inhibiting said circuit path during a second time interval; said second integrated circuit device includes second floating switching means having an input terminal coupled to the logic circuit of a second integrated circuit device, an output terminal connected to the external terminal of said second integrated circuit device, and a control terminal to which a control signal is applied, for inhibiting a circuit path therethrough between the input and output terminals thereof during said first time interval and for providing a circuit path therethrough between the input and output terminals thereof during said second time interval; and wherein the external terminalS of said first and second integrated circuit devices are electrically connected to each other by way of a conductor, whereby signals corresponding to the outputs of said logic circuits of said first and second integrated circuit devices separately appear on said conductor during said first and second time intervals.

Claim 23

The improvement according to claim 19, wherein said first integrated circuit device includes a first OR gate having first and second inputs and an output, the first input of said first OR gate being switchably connected to the connected outputs of said first and second floating switching means during said second time interval, and the second input of said first OR gate being switchably connected to the input of said first floating switching means during said first time interval; and said second integrated circuit device includes a second OR gate having first and second inputs and an output, the first input of said second OR gate being switchably connected to the connected outputs of said first and second floating switching means during said first time interval, and the second input of said second OR gate being switchably connected to the input of said second floating switching means during said second time interval.

Claim 24

The improvement according to claim 20, wherein each logic circuit is a ratioless type logic circuit and wherein each OR circuit has an output switch supplying the output thereof during said first time interval.

Claim 25

The improvement according to claim 20, wherein said first and second time intervals are defined by respective two-phase clock pulses.

Claim 26

The improvement according to claim 20, wherein said first time interval is delayed in time relative to said second time interval and both time intervals are repeated for each integrated circuit device, so that the inputs of each OR gate are sequentially connected to said floating switching means.

Claim 27

The improvement according to claim 20, wherein each of said OR circuits includes means for storing the signal supplied to the first and second inputs thereof.

Claim 28

The improvement according to claim 24, wherein the readout of the signal stored in each OR circuit is effected during one of said first and second time intervals.

Claim 29

The improvement according to claim 20, wherein each integrated circuit is switchably connected between the first input of the OR gate thereof and the output of the floating switching means thereof.

Claim 30

The improvement according to claim 26, wherein said first time interval is delayed in time relative to said second time interval and both time intervals are repeated for each integrated circuit device so that the inputs of each OR gate are sequentially connected to said floating switching means.