Method and circuitry for decoding a high density bar code

Claim 3

The method claimed in claim 1 wherein the categorizing step includes the steps of: generating a numerical ratio proportional to the displacement between the leading edges of the spaces in a module to a displacement between the leading edge of the second space and the trailing end of the module; and generating a numerical ratio proportional to the sum of the widths of the first space and second bar to the displacement between the leading edges of the first and second bar.

Claim 4

The method claimed in claim 2 including the further step of generating a numerical ratio proportional to the width of the first bar to the width of the second space, said numerical ratio for resolving ambiguities between previously generated ratios.

Claim 5

Circuitry for decoding a high-density multiple bar code in which each numeral is represented in the code by a module comprising a pair of bars and spaces, each bar and space hAving a particular width for each numeral, total widths of the bars and spaces in each module being equal for all numerals, said circuitry comprising: scanning means for scanning the bar code representation and for generating electrical signals representing the transition points between said bars and spaces; logic circuitry responsive to said scanning means for generating a plurality of unique signals indicative of the time required to scan between adjacent leading edges of the spaces, between adjacent leading and adjacent lagging edges of the bars within the modules, and the widths of each bar and space within the module; and comparison circuitry coupled to said logic circuitry and responsive to the signals generated therein for comparing selected pairs of said signals and for generating output signals representing the numerals scanned by said scanning means, said comparison circuitry including ramp circuitry coupled to said logic circuitry for developing analog ramp voltage levels proportional to each of said selected pairs of signals, and ratio circuitry coupled to said ramp circuitry for generating binary output signals indicating which of said ramp voltages is at a higher level.

Claim 6

Circuitry for decoding a high-density multiple bar code in which each numeral is represented in the code by a module comprising a pair of bars and spaces, each bar and space hAving a particular width for each numeral, total widths of the bars and spaces in each module being equal for all numerals, said circuitry comprising: scanning means for scanning the bar code representation and for generating electrical signals representing the transition points between said bars and spaces; logic circuitry responsive to said scanning means for generating a plurality of unique signals indicative of the time required to scan between adjacent leading edges of the spaces, between adjacent leading and adjacent lagging edges of the bars within the modules, and the widths of each bar and space within the module; and comparison circuitry coupled to said logic circuitry and responsive to the signals generated therein for comparing selected pairs of said signals and for generating output signals representing the numerals scanned by said scanning means, said comparison circuitry including ramp circuitry coupled to said logic circuitry for developing analog ramp voltage levels proportional to each of said selected pairs of signals, and ratio circuitry coupled to said ramp circuitry for generating binary output signals indicating which of said ramp voltages is at a higher level.

Claim 7

The circuitry claimed in claim 4 wherein said comparison circuitry further included decision circuitry coupled to said ramp circuitry for developing decision points in said analog ramp voltage levels at which the binary output signals of said ratio circuitry will change.

Claim 8

The circuitry claimed in claim 4 wherein said comparison circuitry is coupled to said logic circuitry for comparing signals representing displacements between leading edges of the spaces with those representing the lagging edges of the bars in a module, and signals representing the sum of the widths of first space and second bar with the displacement between leading edges of the bars in the module.

Claim 9

The circuitry claimed in claim 6 wherein said comparison circuitry is coupled to the logic circuitry for comparing signals representing the width of the middle bar with the signal representing the width of the middle space in a module.

Claim 10

The circuitry claimed in claim 6 wherein said scanning means includes an optical scanner, and an edge detector coupled to said scanner for generating electrical pulses representing the transition points between spaces and bars in the scanned module.

Claim 11

The circuitry claimed in claim 8 wherein said logic circuitry includes a two-stage binary counter responsive to the electrical pulses generated by said edge detector.

Claim 12

The circuitry claimed in claim 9 further including a shift register coupled to receive and hold the binary output signals generated by said comparison circuitry.