Synchronous/asynchronous phase lock circuit for a digital vertical sync system

Claim 2

In a digital vertical synchronization system of the type including a source of locally generated vertical sync pulses comprising counting means for counting horizontal sync pulses and means for producing a local vertical sync pulse after counting a predetermined number of horizontal sync pulses, said source of locally generated vertical sync pulses coupled to and driving a vertical sweep system not including a free-running vertical oscillator, said vertical synchronization system further including a source of derived vertical sync pulses developed from a received television signal and a synchronization phase lock system including gating means for rephasing the locally generated vertical sync pulses to bring them into coincidence with the derived vertical sync pulses, the improvement comprising: detection means coupled to said counting means for establishing an interval by detecting predetermined minimum and maximum count values, and mode selection means including a selector switch anD a plurality of mode gates for alternatively operating said vertical sync system in synchronous or asynchronous modes, said plurality of mode gates, when in said asynchronous mode, rendering said detection means effective and conditioning said gating means for rephasing each locally generated vertical sync pulse for coincidence with a derived vertical pulse occurring within said interval.

Claim 3

The digital vertical synchronization system of claim 1 wherein said detection means includes means for producing a local vertical sync pulse at the end of said interval in event of non-occurrence of a derived vertical sync pulse within said interval.

Claim 4

The digital vertical synchronization system of claim 2 wherein said detection means comprise first and second NAND gates coupled to said counting means, said first NAND gate responding whenever said counting means attains said maximum count value and said second NAND gate responding whenever said counting means attains said minimum count value.

Claim 5

The digital vertical synchronization system of claim 3 wherein said source of locally generated vertical sync pulses further includes recognition means for recognizing said predetermined number of horizontal sync pulses; one of said plurality of mode gates being coupled to said recognition means for disabling said recognition means when in said asynchronous mode.

Claim 6

The digital vertical synchronization system of claim 4 wherein said recognition means includes a third NAND gate and wherein said one mode gate includes a fourth NAND gate, said third NAND gate having an input coupled to said counting means and an output coupled to said fourth NAND gate.

Claim 7

The digital vertical synchronization system of claim 5 wherein said plurality of mode gates further includes a fifth NAND gate coupled to said second NAND gate for rendering said second NAND gate effective in said asynchronous mode.

Claim 8

The digital vertical synchronization system of claim 6 wherein said plurality of mode gates further includes a NOR gate interconnected with said synchronization phase lock system for conditioning said gating means for rephasing each locally generated vertical sync pulse for coincidence with said derived vertical pulse occurring within said interval.

Claim 9

In a digital vertical sync system of the type including a horizontal sync pulse-driven source of locally generated vertical sync pulses coupled to and driving a vertical sweep system and a source of derived vertical sync pulses developed from a received television signal, a synchronization phase lock system including circuit means coupled to the source of derived vertical sync pulses for developing a control voltage having a first level during the sync portions of said derived vertical sync pulses conditioning said counter means to count up toward a maximum confidence level and a second level during the trace portions conditioning said counter means to count down toward a minimum confidence level, counter means coupled to the circuit means and to the source of locally generated vertical sync pulses for counting up to said maximum confidence level during coincidence between the locally generated vertical sync pulses and the derived vertical sync pulses and for counting down to said minimum confidence level during noncoincidence therebetween, gating means coupled between said counter means and said source of locally generated vertical sync pulses for rephasing the local sync pulses to bring them into time coincidence with the derived sync pulses by generating a reset signal coincident with the first locally generated vertical sync pulse occurring during said first level of said control voltage subsequent to said counter means reaching said minimum confidence level, feedback means developing an override signal whenever said counter means reaches said maximum confidence level for forcing said counter means to count down upon receipt of the next said locally generated vertical sync pulse irrespective of the level oF said control voltage, the improvement comprising: mode selection switch means for alternately operating said vertical sweep system in synchronous and asynchronous modes, said switch means conditioning said gating means for rephasing each locally generated vertical sync pulse to coincide with a derived vertical sync pulse when said vertical sweep system is operating in said asynchronous mode; and noise immunizing means coupled to said gating means and effective when said system is in said asynchronous mode, comprising a NAND gate coupled between said source of locally generated sync pulses and said gating means, said NAND gate developing a reset inhibit signal at all times other than an interval beginning with a predetermined minimum number of horizontal sync pulses and ending a predetermined maximum number of horizontal sync pulses later, said reset inhibit signal being coupled to said gating means for inhibiting the development of said reset signals at times other than during said interval, said predetermined interval corresponding generally to the time of occurrence of said derived vertical sync pulse.

Claim 10

In a digital vertical sync system of the type including a horizontal sync pulse-driven source of locally generated vertical sync pulses coupled to and driving a vertical sweep system and a source of derived vertical sync pulses developed from a received television signal, a synchronization phase lock system including circuit means coupled to the source of derived vertical sync pulses for developing a control voltage having a first level during the sync portions of said derived vertical sync pulses conditioning said counter means to count up toward a maximum confidence level and a second level during the trace portions conditioning said counter means to count down toward a minimum confidence level, counter means coupled to the circuit means and to the source of locally generated vertical sync pulses for counting up to said maximum confidence level during coincidence between the locally generated vertical sync pulses and the derived vertical sync pulses and for counting down to said minimum confidence level during noncoincidence therebetween, gating means coupled between said counter means and said source of locally generated vertical sync pulses for rephasing the local sync pulses to bring them into time coincidence with the derived sync pulses by generating a reset signal coincident with the first locally generated vertical sync pulse occurring during said first level of said control voltage subsequent to said counter means reaching said minimum confidence level, feedback means developing an override signal whenever said counter means reaches said maximum confidence level for forcing said counter means to count down upon receipt of the next said locally generated vertical sync pulse irrespective of the level oF said control voltage, the improvement comprising: mode selection switch means for alternately operating said vertical sweep system in synchronous and asynchronous modes, said switch means conditioning said gating means for rephasing each locally generated vertical sync pulse to coincide with a derived vertical sync pulse when said vertical sweep system is operating in said asynchronous mode; and noise immunizing means coupled to said gating means and effective when said system is in said asynchronous mode, comprising a NAND gate coupled between said source of locally generated sync pulses and said gating means, said NAND gate developing a reset inhibit signal at all times other than an interval beginning with a predetermined minimum number of horizontal sync pulses and ending a predetermined maximum number of horizontal sync pulses later, said reset inhibit signal being coupled to said gating means for inhibiting the development of said reset signals at times other than during said interval, said predetermined interval corresponding generally to the time of occurrence of said derived vertical sync pulse.

Claim 11

The digital vertical sync system as claimed in claim 8 wherein said noise immunizing means further includes a NAND gate for developing said reset signals at the end of said interval whenever said derived sync pulse does not occur during said interval.

Claim 12

The digital vertical sync system as claimed in claim 8 wherein said switch means develops first and second complementary control signals for application to said gating means and said noise immunizing means, said complementary control signals conditioning said digital synchronization system to either synchronous operation or asynchronous operation.

Claim 13

The digital vertical sync system as claimed in claim 10 further including a NOR gate interposed between said gating means and said counter means and a NAND gate interposed between said noise immunizing means and said gating means, said first complementary control signal being applied to said NOR gate during asynchronous operation for maintaining said gating means ready to generate said reset signal for each said derived vertical sync pulse during each vertical field, and said second complementary control signal being coupled to said NAND gate for disabling said noise immunizing means during synchronous operation.