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US3914855A
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Methods for making MOS read-only memories
Assignee: AT&T Inc
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Filing: 1974-05-09
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Granted: 1975-10-28
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Expires: 1994-05-09
Abstract
Abstract An MOS read-only memory comprises a matrix array of IGFETs which are initially made all to be operable. The array is encoded by etching apertures in the gate electrodes of selected devices and ion implanting impurities through the apertures to render the selected devices inoperative, thus defining digital ''''O''''s.
Inventors
- 👤 Glen Trenton Cheney
- 👤 John Richard Edwards
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:09
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/36; G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/106
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
133 words
A method for making a read-only memory comprising the steps of: forming a matrix array of operable IGFETs comprising the steps of forming an array of source and drain regions on a surface of a semiconductor substrate; forming thin gate oxide layers overlying channel regions between adjacent source and drain regions; forming a thick insulating layer over a major part of the remaining surface; forming parallel gate electrodes each perpendicular to the array of source and drain regions and each overlying the thick insulative layer and successive gate oxide layers; and encoding the array by rendering selected IGFETs inoperable; the foregoing step comprising the step of removing that portion of the gate electrode immediately overlying the thin gate oxide layer of the selected IGFET without severing the entire width of the gate electrode.
Claim 2
Independent Claim
133 words
A method for making a read-only memory comprising the steps of: forming a matrix array of operable IGFETs comprising the steps of forming an array of source and drain regions on a surface of a semiconductor substrate; forming thin gate oxide layers overlying channel regions between adjacent source and drain regions; forming a thick insulating layer over a major part of the remaining surface; forming parallel gate electrodes each perpendicular to the array of source and drain regions and each overlying the thick insulative layer and successive gate oxide layers; and encoding the array by rendering selected IGFETs inoperable; the foregoing step comprising the step of removing that portion of the gate electrode immediately overlying the thin gate oxide layer of the selected IGFET without severing the entire width of the gate electrode.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein: the removing step comprises the step of masking all but selected portions of the gate electrodes and etching the selected portions.
Claim 4
Dependent Claim
82 words
The method of claim 2 wherein: the gate electrode forming step comprises the step of forming gate electrodes each having a larger width than those of the thin gate oxide layers it overlies; and the removing step comprises the step of etching apertures in the gate electrodes each having a width wider than that of the corresponding gate oxide layer and narrower than the gate electrode, thereby forming two parallel bridge conductors each bypassing gate electrode current past each selected inoperable IGFET.
Claim 5
Dependent Claim
45 words
The method of claim 2 further comprising the step of: irradiating the matrix array with ions of sufficient energy to penetrate the exposed thin gate oxide regions to the semiconductor substrate but of insufficient energy to penetrate either the gate electrodes or the thick oxide.
Claim 6
Dependent Claim
32 words
The method of claim 4 wherein: the ions are of a conductivity type which would discourage surface channel conduction between adjacent source and drain regions in response to an operating gate voltage.
Claim 7
Dependent Claim
21 words
The method of claim 5 wherein: the ions are of a conductivity type opposite that of the source and drain regions.
Claim 8
Dependent Claim
59 words
The method of claim 6 wherein: the mask step comprises the step of coating the matrix array with a photoresist that is sensitive to light, resistant to the etchant used in the etch step, and substantially non-permeable with respect to the projected ions, whereby the mask prevents penetration of the ions except at the selected thin gate oxide regions.
Claim 9
Dependent Claim
14 words
The method of claim 7 wherein: the photoresist is at least 5,000 Angstroms thick.
Claim 10
Dependent Claim
32 words
The method of claim 6 wherein: the substrate is silicon, the ions are projected at an energy of 30 to 500 Kev, and the ion dose is 1012 to 1015 ions/sq. cm.
Claim 11
Dependent Claim
36 words
The method of claim 9 wherein: after the ion implant, the matrix array is maintained at a temperature below about 600*C, whereby there is no diffusion of the implanted ions or annealing of the implanted substrate.
Claim 12
Independent Claim
174 words
A method for making a read-only memory comprising the steps of: forming a plurality of semiconductor regions of one conductivity type on the upper surface of a wafer portion of the opposite conductivity type; forming a plurality of thin gate oxide layers over the wafer portion between adjacent semiconductor regions; forming a thick oxide layer over substantially the entire remaining surface of the wafer portion; forming over each of the thin gate oxide layers a gate electrode; encoding the array comprising the steps of coating the array with photoresist, forming a mask having an aperture at locations corresponding to specific binary digits, photolithographically exposing and etching the photoresist at locations corresponding to aperture locations, and etching apertures in the gate electrodes at locations corresponding to the specific binary digits, each gate electrode aperture substantially completely exposing an underlying thin gate layer; and irradiating the array with subatomic particles of a type that discourages conduction between adjacent semiconductor regions, the irradiation being of a sufficient energy level to penetrate the exposed thin gate oxide layers.
Claim 13
Independent Claim
174 words
A method for making a read-only memory comprising the steps of: forming a plurality of semiconductor regions of one conductivity type on the upper surface of a wafer portion of the opposite conductivity type; forming a plurality of thin gate oxide layers over the wafer portion between adjacent semiconductor regions; forming a thick oxide layer over substantially the entire remaining surface of the wafer portion; forming over each of the thin gate oxide layers a gate electrode; encoding the array comprising the steps of coating the array with photoresist, forming a mask having an aperture at locations corresponding to specific binary digits, photolithographically exposing and etching the photoresist at locations corresponding to aperture locations, and etching apertures in the gate electrodes at locations corresponding to the specific binary digits, each gate electrode aperture substantially completely exposing an underlying thin gate layer; and irradiating the array with subatomic particles of a type that discourages conduction between adjacent semiconductor regions, the irradiation being of a sufficient energy level to penetrate the exposed thin gate oxide layers.
Claim 14
Dependent Claim
23 words
The method of claim 11 wherein: the subatomic particles are ions of a conductivity type opposite that of the source and drain regions.
Claim 15
Dependent Claim
47 words
The method of claim 11 wherein: the subatomic particles are ions of a conductivity type opposite that of the semiconductor regions; the substrate is silicon; the ions are prOjected at an energy of 30 to 500 Kev; and the ion dose is 1012 to 1015 ions/sq. cm.
Claim 16
Dependent Claim
32 words
The method of claim 13 wherein: the substrate is silicon, the ions are projected at an energy of 30 to 500 Kev, and the ion dose is 1012 to 1015 ions/sq. cm.
Claim 17
Independent Claim
203 words
A method for making a read-only memory comprising the steps of: forming a parallel array of semiconductor stripes of one conductivity type on the upper surface of a wafer of the opposite conductivity type; forming a plurality of thin gate oxide layers over the wafer between adjacent semiconductor stripes, the gate oxide layers being arranged in rows perpendicular to the semiconductor stripes; forming a thick oxide layer over substantially the entire remaining upper surface of the wafer; forming a plurality of parallel gate electrode stripes each perpendicular to the semiconductor stripes and each overlying successive thin gate oxide layers; encoding the array comprising the steps of coating the array with photoresist, forming a mask having an aperture at locations corresponding to digital ''''0''''s, photolithographically exposing and etching the photoresist at locations corresponding to the aperture locations, and etching apertures in the gate electrode stripes at locations corresponding to digital ''''0''''s, each gate electrode aperture substantially completely exposing an underlying thin gate oxide layer without severing the gate electrode; and irradiating the array with subatomic particles of a type that discourages conduction between adjacent source and drain regions, the irradiation being of a sufficient energy level to penetrate the exposed thin gate oxide layers.
Claim 18
Independent Claim
203 words
A method for making a read-only memory comprising the steps of: forming a parallel array of semiconductor stripes of one conductivity type on the upper surface of a wafer of the opposite conductivity type; forming a plurality of thin gate oxide layers over the wafer between adjacent semiconductor stripes, the gate oxide layers being arranged in rows perpendicular to the semiconductor stripes; forming a thick oxide layer over substantially the entire remaining upper surface of the wafer; forming a plurality of parallel gate electrode stripes each perpendicular to the semiconductor stripes and each overlying successive thin gate oxide layers; encoding the array comprising the steps of coating the array with photoresist, forming a mask having an aperture at locations corresponding to digital ''''0''''s, photolithographically exposing and etching the photoresist at locations corresponding to the aperture locations, and etching apertures in the gate electrode stripes at locations corresponding to digital ''''0''''s, each gate electrode aperture substantially completely exposing an underlying thin gate oxide layer without severing the gate electrode; and irradiating the array with subatomic particles of a type that discourages conduction between adjacent source and drain regions, the irradiation being of a sufficient energy level to penetrate the exposed thin gate oxide layers.
Claim 19
Dependent Claim
35 words
The method of claim 15 wherein: after the ion implant, the array is maintained at a temperature below about 600*C, whereby there is no diffusion of the implanted ions or annealing of the implanted substrates.
References Cited (Backward Citations)
US3377513A
Cited
US3423822A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-27 | 1979-04-28 | 1979-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-27 | 1983-04-28 | 1983-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-27 | 1987-04-28 | 1987-10-28 | $7700.00 | Window Closed / Lapsed |