Electronic data-processing system and method of operating same

Claim 3

A method as defined in claim 1, comprising the step of including in each instruction word an additional section evaluated jointly with the data/address section of a routing instruction in controlling said exchange of information.

Claim 4

A method as defined in claim 2, comprising the step of limiting said additional section to a single bit.

Claim 5

A method as defined in claim 3, further comprising the step of defining each instruction word by n bits, said discriminating bit being the nth bit, said classification section encompassing a group of highest-ranking bits including said discriminating bit, said data/address section encompassing a group of lowest-ranking bits, said operation/address section encompassing a group of intermediate bits, the single bit of said additional section being inserted between said data/address and operation/address sections.

Claim 6

A method as defined in claim 4 wherein n 12, comprising the step of including in said classification section the four highest-ranking bits, said operation/address section encompassing three intermediate bits, said data/address section encompassing the four lowest-ranking bits.

Claim 7

A method as defined in claim 1, comprising the step of including in said jump instructions a plurality of jump-forward instructions and a jump-back instruction, the latter being distinguished from said jump-forward instructions by the presence of a special code in said classification section.

Claim 8

A method as defined in claim 6, comprising the step of using the entire instruction word to locate a new word to be read out from said subprogram memory in the case of a jump-forward instruction.

Claim 9

A method as defined in claim 6, comprising the step of distinguishing numerical instructions from routing instructions by the presence of said special code in the classification section thereof.

Claim 10

A method as defined in claim 1, comprising the step of identifying in the data/address section of a routing instruction an item of information entered in said storage means at an original address, part of the operation/address section of said routing instruction being used to identify another item of information entered in said storage means at an address adjoining said original address.

Claim 11

A method as defined in claim 9, comprising the step of defining said part of the operation/address section by a pair of bits enabling selective identification of a second address immediately preCeding and a third address immediately following said original address.

Claim 12

In an electronic data-processing system, in combination: a subprogram memory for the storage of a multiplicity of binary instruction words of predetermined length to be read out in succession; extraction means for the parallel readout of the bits of each instruction word from said subprogram memory, said extraction means including a data/address section, an operation/address section and a classification section; decoding means for an operation code forming part of each instruction word read out by said extraction means; selection means for addressing said subprogram memory to alter the readout sequence thereof; control means for said selection means; processing means including an accumulator for digital information, storage means connected across said accumulator in a first loop, input/output means connected across said accumulator in a second loop, and interim register means connected across said accumulator in a third loop said third loop having branches leading to said storage means and to said input/output means for enabling selective exchange of information between said accumulator, said storage means and said input/output means under the control of said decoding means; circuitry for the selective transmission of bits from any read-out instruction word to said decoding means, selection means and processing means, said circuitry comprising one channel extending from the data/address section of said extraction means to said accumulator and in parallel therewith to said interim register means and to said selection means, another channel extending from the operation/address section of said extraction means to said selection means and in parallel therewith to said decoding means, and a further channel extending from the classification section of said extraction means to said control means and in parallel therewith to said decoding means; signal paths leading from said decoding means to said processing means and to said subprogram memory for (a) enabling said accumulator to receive data via said one channel in the presence of an operation code in said further channel identifying a numerical instruction, (b) enabling said interim register means to receive a first address code via said one channel in the presence of an operation code in said further channel identifying a routing instruction, and (c) supplementing said first address code with a second address code transmitted to said selection means via said other channel in the presence of a discriminating bit of predetermined binary value appearing in said further channel to identify a jump instruction, said control means enabling said selection means to decode said second address code for addressing said subprogram memory in response to said discriminating bit; and timing means for establishing a recurrent readout cycle for said subprogram memory.

Claim 13

In an electronic data-processing system, in combination: a subprogram memory for the storage of a multiplicity of binary instruction words of predetermined length to be read out in succession; extraction means for the parallel readout of the bits of each instruction word from said subprogram memory, said extraction means including a data/address section, an operation/address section and a classification section; decoding means for an operation code forming part of each instruction word read out by said extraction means; selection means for addressing said subprogram memory to alter the readout sequence thereof; control means for said selection means; processing means including an accumulator for digital information, storage means connected across said accumulator in a first loop, input/output means connected across said accumulator in a second loop, and interim register means connected across said accumulator in a third loop said third loop having branches leading to said storage means and to said input/output means for enabling selective exchange of information between said accumulator, said storage means and said input/output means under the control of said decoding means; circuitry for the selective transmission of bits from any read-out instruction word to said decoding means, selection means and processing means, said circuitry comprising one channel extending from the data/address section of said extraction means to said accumulator and in parallel therewith to said interim register means and to said selection means, another channel extending from the operation/address section of said extraction means to said selection means and in parallel therewith to said decoding means, and a further channel extending from the classification section of said extraction means to said control means and in parallel therewith to said decoding means; signal paths leading from said decoding means to said processing means and to said subprogram memory for (a) enabling said accumulator to receive data via said one channel in the presence of an operation code in said further channel identifying a numerical instruction, (b) enabling said interim register means to receive a first address code via said one channel in the presence of an operation code in said further channel identifying a routing instruction, and (c) supplementing said first address code with a second address code transmitted to said selection means via said other channel in the presence of a discriminating bit of predetermined binary value appearing in said further channel to identify a jump instruction, said control means enabling said selection means to decode said second address code for addressing said subprogram memory in response to said discriminating bit; and timing means for establishing a recurrent readout cycle for said subprogram memory.

Claim 14

The combination defined in claim 11 wherein said interim register means comprises a pair of register halves with respective control inputs for writing and reading, said circuitry further comprising a lead extending from said extraction means to said interim register means for alternately energizing said control inputs in response to respective values of an additional bit of a routing instruction read out from said subprogram memory.

Claim 15

The combination defined in claim 12 wherein said lead has a branch extending to said selection means for delivering said additional bit thereto as part of said second address code in the case of a jump instruction.

Claim 16

The combination defined in claim 11 wherein said storage means and said input/output means are respectively provided with a first and a second address register connected to receive multibit items of digital information from said accumulator via said interim register means, at least one of said address registers having a storage capacity for a number of bits several times that of any of said multibit iTems, said interim register means being provided with address-modification means controlled by said decoding means and by said timing means for altering the numerical value of an item temporarily stored in said interim register means and for suequentially transmitting both the original and the altered numerical value of the stored item to said one of said address registers during one readout cycle in response to a predetermined bit value in a part of a routing instruction concurrently transmitted to said decoding means.

Claim 17

The combination defined in claim 14 wherein said address-modification means comprises a feedback loop extending from an output of said interim register means to an input thereof, a full adder in said feedback loop, and bistable means settable by said decoding means for introducing a predetermined supplemental numerical value into said full adder.

Claim 18

The combination defined in claim 14 wherein said timing means includes a shift register, pulse-generating means working into said shift register and circuit means connected to certain stages of said shift register for deriving therefrom a plurality of control signals for said address-modification means.

Claim 19

The combination defined in claim 11 wherein said processing means further includes an arithmetic unit connected across said accumulator in a fourth loop for logically combining the contents of said accumulator with selected items of information of said storage means under the control of said decoding means.

Claim 20

The combination defined in claim 17 wherein said processing means includes electronic gate means controlled by said decoding means for selectively connecting said fourth loop to said one channel in the presence of a numerical instruction.

Claim 21

The combination defined in claim 17 wherein said fourth loop has a feedback branch including a buffer register connected to receive digital information from said storage means, said input/output means, said interim register means and said arithmetic unit for recirculation to the latter.

Claim 22

The combination defined in claim 19 wherein said third loop includes a pair of conductor multiples for respectively delivering complementary information from said interim register means to an inverting and a noninverting input of said accumulator, one of said conductor multiples extending to said buffer register.

Claim 23

The combination defined in claim 17, further comprising signaling means extending from said arithmetic unit to said control means for informing same of the completion of a logical operation.

Claim 24

The combination defined in claim 11 wherein said selection means includes a first and a second multistage register having corresponding stages interconnected, an address decoder for said subprogram memory connected in parallel with said second multistage register to the stages of said first multistage register, and electronic switch means responsive to said control means; said one channel and said other channel together comprising a multiplicity of conductors normally connected through said electronic switch means to associated stage inputs of said first multistage register for delivering thereto respective bits of said second address code in the presence of said discriminating bit and of bit combinations in said further channel identifying a jump-forward instruction, said second multistage register having stage outputs connectable through said electronic switch means to respective stage inputs of said first multistage register, said control means being responsive to said discriminating bit to command the transfer of the contents of said first multistage register to said second multistage register and to said address decoder, said control means being further responsive to a special code in said further channel identifying a jump-back instruction to reverse said electronic switch means for retransferring a previously transferred address from said second to said first multistage register for another transmission to said address decoder.

Claim 25

The cOmbination defined in claim 11 wherein said timing means comprises individual timers with mutually independent operating cycles for said subprogram memory, said decoding means, said storage means and said input/output means, said timers being provided with connections for correlating the starting points of their respective operating cycles.